zl50404 Zarlink Semiconductor, zl50404 Datasheet - Page 23

• Manufacturer Part Number: zl50404
• Description: Lightly Managed/unmanaged 5-port 10/100m Ethernet Switch
• Manufacturer: Zarlink Semiconductor

3.1
3.1.1
The ZL50404 has many programmable parameters, covering such functions as QoS weights, VLAN control, and
port mirroring setup. In managed mode, the CPU interface provides an easy way of configuring these parameters.
The parameters are contained in 8-bit configuration registers. The device allows indirect access to these registers,
as follows:
•
•
In serial mode, the address, command and data are shifted in serially. To access the configuration registers,
only one “index” register (addresses 000b) needs to be written with the configuration register address. The
desired data can be written into or read from the “data” register (address 010b).
•
To indirectly configure the register addressed by the index register, a “data” register (address 010b) must be
written with the desired 8-bit data.
Register Configuration, Frame Transmission, and Frame Reception
For example, if “XX” is required to be written to register “YY”, a write of “YY” is required to write to
address “000b” (Index register). Then, a write of “XX” is required to write to address “010b” (Data
Register). This completes the register write and register “YY” will contain the value of “XX”.
Index Reg 1
(Addr = 1)
Register Configuration
16-bit Address
Index Reg 0
(Addr = 0)
8-bit Data Bus
Config Data
(Addr = 2)
Registers
Inderect
Internal
Access
Reg
Figure 3 - Overview of the SSI Interface
3-bit Address Bus
CPU Frame Reg
8/16-bit Data Bus
Processor
CPU frame
Address
Receive
(Addr = 3)
Zarlink Semiconductor Inc.
FIFO
Serial Out
Synchronous Serial Interface
CPU frame
Transmit
ZL50404
FIFO
23
Serial In
16-bit Data Bus
Command/
Status Reg
(Addr = 4)
Strobe
I/O Data MUX
Interrupt
INT CS W R
Interrupt
(Addr = 5)
Interrupt
Reg
8/16-bit Data Bus
Command 1
Receive
Control
FIFO
Command 1 Reg
(Addr = 6)
Command 1
Control
Transmit
Control
FIFO
Command 2
Command 2
(Addr = 7)
Transmit
Control
Control
Data Sheet
FIFO
Reg