zl50404 Zarlink Semiconductor, zl50404 Datasheet - Page 83

• Manufacturer Part Number: zl50404
• Description: Lightly Managed/unmanaged 5-port 10/100m Ethernet Switch
• Manufacturer: Zarlink Semiconductor

13.3.6.20
I²C Address h0B3+n, CPU Address:h550+n
Accessed by CPU and I²C (R/W)
(Default 00) This register is duplicated eight times from PROTOCOL 0~7 and allows the CPU to define eight
separate protocols.
13.3.6.21
I²C Address h0BB, CPU Address 558
Accessed by CPU and I²C (R/W)
User Defined Logical Ports and Well Known Ports
The ZL50404 supports classifying packet priority through layer 4 logical port information. It can be setup by 8 Well
Known Ports, 8 User Defined Logical Ports, and 1 User Defined Range. The 8 Well Known Ports supported are:
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23
512
6000
443
111
22555
22
554
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
Bits[7:0]:
Bits[0]:
Bits[1]:
Bits[2]:
Bits[3]:
Bits[4]:
Bits[5]:
Bits[6]:
Bits[7]:
USER_PROTOCOL_n – User Define Protocol 0~7
USER_PROTOCOL_FORCE_DISCARD – User Define Protocol 0~7 Force Discard
Frame drop priority when TOS field is 3 (Default 0)
Frame drop priority when TOS field is 4 (Default 0)
Frame drop priority when TOS field is 5 (Default 0)
Frame drop priority when TOS field is 6 (Default 0)
Frame drop priority when TOS field is 7 (Default 0)
User Define Protocol
Enable Protocol 0 Force Discard
1 – Enable
0 – Disable
Enable Protocol 1 Force Discard
Enable Protocol 2 Force Discard
Enable Protocol 3 Force Discard
Enable Protocol 4 Force Discard
Enable Protocol 5 Force Discard
Enable Protocol 6 Force Discard
Enable Protocol 7 Force Discard
Zarlink Semiconductor Inc.
ZL50404
83
Data Sheet