zl50404 Zarlink Semiconductor, zl50404 Datasheet - Page 90

• Manufacturer Part Number: zl50404
• Description: Lightly Managed/unmanaged 5-port 10/100m Ethernet Switch
• Manufacturer: Zarlink Semiconductor

13.3.7.4
CPU Address:h603
Accessed by CPU (R/W)
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY, and no VALID; then
program MII command.
13.3.7.5
CPU Address:h604
Accessed by CPU (R/W)
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then
program MII command.
13.3.7.6
CPU Address:h605
Accessed by CPU (R/W)
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then
program MII command.
Bit [5]:
Bit [6]:
Bit [7]:
Bits[7:0]:
Bits[7:0]:
Bit [4:0]
Bit [6:5]
Bit [7]
MIIC0 – MII Command Register 0
MIIC1 – MII Command Register 1
MIIC2 – MII Command Register 2
Report to CPU
0 – Disable (Default)
1 – Enable
When disable new MAC address report or aging reports are disable for all
ports. When enable, register SE_OPMODE is used to enable/disable
selectively each function.
MII Management State Machine
0: Enable (Default)
1: Disable
This bit must be set so that there is no contention on the MDIO bus between
MII Management state machine and MIIC & MIID PHY register accesses.
MCT Link List structure
0 – Enable (Default)
1 – Disable
MII Command Data [7:0]
MII Command Data [15:8]
REG_AD – Register PHY Address
OP – Operation code “10” for read command and “01” for write command
Reserved
Zarlink Semiconductor Inc.
ZL50404
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Data Sheet