zl50404 Zarlink Semiconductor, zl50404 Datasheet

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... Down to 16 kbps Rate Control granularity 2 C EEPROM ZL50404 MII 5-Port 10/100M Ethernet Switch RMII / MII / GPSI Quad 10/100 PHY Figure 1 - System Block Diagram 1 Zarlink Semiconductor Inc. ZL50404 Data Sheet August 2004 Ordering Information 208 Pin LBGΑ -40°C to +85°C 10/100 PHY ...

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... Backpressure flow control for Half Duplex ports • Hardware auto-negotiation through MII management interface (MDIO) for Ethernet ports • Built-in reset logic triggered by system malfunction • Built-In Self Test for internal SRAM • IEEE-1149.1 (JTAG) test port ZL50404 2 Zarlink Semiconductor Inc. Data Sheet ...

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... UDP/TCP logical port fields in IP packets. The ZL50404 recognizes a total of 16 UDP/TCP logical ports, 8 hard-wired and 8 programmable (including one programmable range). The ZL50404 provides the ability to monitor a link, detect a simple link failure, and provide notification of the failure to the CPU. The CPU can then failover that link to an alternate link. ...

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... Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1 Search Engine Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2 Basic Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3 Search, Learning, and Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3.1 MAC Search 5.3.2 Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3.3 Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.4 MAC Address Filtering 5.5 Protocol Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.6 Logical Port Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.7 Quality of Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.8 Priority Classification Rule 5.9 Port Based VLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.0 Frame Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 ZL50404 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...

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... JTAG Test Clock (TCK) speed requirements 11.2 Clock Generation 11.2.1 MDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 11.2.2 SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 11.2.3 Ethernet Interface Clocks 12.0 Hardware Statistics Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12.1 Hardware Statistics Counters List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12.2 IEEE 802.3 HUB Management (RFC 1516 12.2.1 Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 12.2.1.1 ReadableOctet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 12.2.1.2 ReadableFrame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 12.2.1.3 FCSErrors 12.2.1.4 AlignmentErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 12.2.1.5 FrameTooLongs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 ZL50404 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...

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... CRCAlignErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.4.1.6 UndersizePkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.4.1.7 OversizePkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.4.1.8 Fragments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.4.1.9 Jabbers 12.4.1.10 Collisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.4.1.11 Packet Count for Different Size Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.5 Miscellaneous Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.0 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.1 ZL50404 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.2 Directly Accessed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13.2.1 INDEX_REG0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13.2.2 DATA_FRAME_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13.2.3 CONTROL_FRAME_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13.2.4 COMMAND&STATUS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13.2.5 Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 13.2.6 Control Command Frame Buffer1 Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 13.2.7 Control Command Frame Buffer2 Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 13 ...

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... C1RS – Class 1 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 13.3.6.10 C2RS – Class 2 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 13.3.6.11 C3RS – Class 3 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 13.3.6.12 AVPML – VLAN Tag Priority Map 13.3.6.13 AVPMM – VLAN Priority Map 13.3.6.14 AVPMH – VLAN Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.3.6.15 AVDM – VLAN Discard Map ZL50404 Table of Contents 7 Zarlink Semiconductor Inc. Data Sheet ...

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... MIRROR_DEST_MAC[5:0] – Mirror Destination MAC Address 0 13.3.8.3 MIRROR_SRC _MAC[5:0] – Mirror Source MAC Address 0 13.3.8.4 RMAC_MIRROR0 – RMAC Mirror 13.3.8.5 RMAC_MIRROR1 – RMAC Mirror 13.3.9 (Group 8 Address) Per Port QOS Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.3.9.1 FCRn – Port 0~3,8,9 Flooding Control Register ZL50404 Table of Contents 8 Zarlink Semiconductor Inc. Data Sheet ...

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... AC Characteristics and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 14.4.1 Typical Reset & Bootstrap Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 14.4.2 Reduced Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 14.4.3 Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 14.4.4 General Purpose Serial Interface (7-wire 114 14.4.5 MDIO Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 ZL50404 Table of Contents 9 Zarlink Semiconductor Inc. Data Sheet ...

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... I²C Input Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 14.4.7 Serial Interface Setup Timing 117 14.4.8 JTAG (IEEE 1149.1-2001 118 15.0 Document Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 15.1 July 2003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 15.2 November 2003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 15.3 February 2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 15.4 August 2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 ZL50404 10 Zarlink Semiconductor Inc. Data Sheet ...

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... M2_RX M2_C M2_TX M3_RX M3_C 1.2 Power and Ground Distribution G7-10, H7-10, J7-10, K7-10 GND 3.3V D5, D12, E4, E13, M4, M13, N5 1.8V D9, H4, H13, N7 ZL50404 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD TSTO TSTO TSTO TSTO TSTO ...

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... DATAIN B1 P_INT# Fast Ethernet Access Ports [3:0] MII N4, P4, R4, T4, N1, M[3:0]_RXD[3:0] Input P1, R1, T1, J4, K3, K2, K1, F4, F3, G2, G1 T5, T2, L1, H1 M[3:0]_CRS_DV Input R5, R2, L2, H2 M[3:0]_TXEN ZL50404 I/O 2 Output Serial Clock Line w/ pull up Unmanaged Mode Only 2 I/O- Serial Data Line w/ pull up Unmanaged Mode Only ...

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... M9_MTXCLK Test Interface C11, C10, D10, C9, TSTOUT[15:0] C8, D8, C7, D7, C6, C5, C4, D4, C3, D3, C2, D2 Test Facility C13 TDI ZL50404 I/O Output, slew Ports [3:0] – Transmit Data Bit [3:0] Input Ports[3:0] – Collision w/ pull down Input or Output Ports[3:0] – Transmit Clock w/ pull up This pin in an output if ECR4Pn[0]='1' Input or Output Ports[3:0] – ...

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... V SS K7-10 Misc. D1 RESIN# C1 RESETOUT# F1 M_MDC F2 M_MDIO R7 M_CLK A13 REF_CLK ZL50404 I/O Input JTAG - Test Reset w/pull up Input JTAG - Test Clock w/pull up Input JTAG - Test Mode State w/pull up Output JTAG - Test Data Out Input Scan Enable. Manufacturing test option. Must be externally Should be externally pulled-down for proper pulled-down operation ...

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... E16, E15, F16, F15, D16, B15, A14 Bootstrap Pins (1= pull up 0= pull down) D2 TSTOUT[0] D3, C2 TSTOUT[2:1] C3 TSTOUT[3] C5, C4, D4 TSTOUT[6:4] ZL50404 I/O N/A Reserved. Leave unconnected. 1 Input (Reset Only) Enable Debounce of STROBE signal Pullup – Enabled Pulldown - Disabled Input (Reset Only) Reserved. Must be pulled up. ...

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... C11, C10, D10 TSTOUT[15:13] R5, R2, L2, H2 M[3:0]_TXEN 1. External pull-up/down resistors are required on all bootstrap pins for proper operation. Recommend 10K for pull-ups and 1K for pull-downs. ZL50404 I/O Input (Reset Only) EEPROM not installed. Pullup: Not installed Pulldown: Installed Input (Reset Only) Manufacturing Option ...

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... Signal Mapping and Internal Pull Up/Down Configuration The ZL50404 Fast Ethernet access ports (0-3) support 3 interface options: RMII, MII & GPSI. The table below summarizes the interface signals required for each interface and how they relate back to the Pin Symbol name shown in the “Ball Signal Description Table” on page 12. It also specifies whether the internal pull up/down resistor is present for each pin in the specific operating mode ...

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... The ZL50404 Fast Ethernet uplink port (port 9) supports 1 interface option: MII. The table below summarizes the interface signals required for each interface, and how they relate back to the Pin Symbol name shown in “Ball Signal Description Table” on page 12. Fast Ethernet Uplink Port ...

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... C EEPROM can be used to configure the device at power-up or reset. TSTOUT[7] selects the EEPROM option. The ZL50404 supports module hotswap on all it's ports. This is enabled via TSTOUT[9]. When enabled, bootstrap pins M[3:0]_TXEN (ports 0-3) are used to specify the module type to support multiple ethernet interfaces during module hotswap ...

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... Frame Engine (FE) and the external physical device (PHY). It has five interfaces: MII, RMII, GPSI (only for 10M), Reverse MII, or Reverse GPSI (only for 10M). The RMAC of the ZL50404 device meets the IEEE 802.3 specification able to operate in either Half or Full Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically retransmit upon collision for total transmissions ...

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... Frame Engine (FE) and the external physical device (PHY). The MMAC implements an MII interface. The MMAC of the ZL50404 device meets the IEEE 802.3 specification able to operate in 10M/100M either Half or Full Duplex mode with a back pressure/flow control mechanism. Furthermore, it will automatically retransmit upon collision for total transmissions ...

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... Heartbeat Packet Generation and Response The ZL50404 provides the ability to monitor a link and detect a simple link failure. The Link Heart Beat (LHB) packet generation module allows simultaneous tracking of all the RMAC ports. Periodically, a LHB message will be sent for each link when inactivity is detected with in a programmable time period reply is not received in a specified amount of time, the failover detection module will identify a point-to-point failure for that link ...

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... Register Configuration The ZL50404 has many programmable parameters, covering such functions as QoS weights, VLAN control, and port mirroring setup. In managed mode, the CPU interface provides an easy way of configuring these parameters. The parameters are contained in 8-bit configuration registers. The device allows indirect access to these registers, as follows: • ...

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... The speed of the serial interface limits management capability. For example, if the system is trying to implement port security, it would require a faster interface between the CPU and the ZL50404, such as the 8/16-bit interface or the serial + MII interface found on the managed device. 3.1.3 ...

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... Start Condition Generated by the master (in our case, the ZL50404). The bus is considered to be busy after the Start condition is generated. The Start condition occurs if while the SCL line is High, there is a High-to-Low transition of the SDA line. Other than in the Start condition (and Stop condition), the data on the SDA line must be stable during the High period of SCL. The High or Low state of SDA can only change when SCL is Low. In addition, when the I² ...

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... I²C protocol. The main difference is that there is no acknowledgment bit after each byte of data transferred. Debounce logic on the clock signal (STROBE) can be turned off to speedup command time bits are used to allow up to eight ZL50404 devices to share the same synchronous serial interface. The ID of each device can be setup by bootstrap. ...

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... STROBE- fall. 3.3.1 Write Command All registers in ZL50404 can be modified through this synchronous serial interface. Once the data has been sent, two extra STOBE clocks must be generated to indicate the end of the write command. The DATAIN line should be held high for these two pulses. ...

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... CPU ports, to map the 8 transmit priorities into 4 multicast queues, the LSB is discarded. The priority mapping can be modified through memory configuration command. The multicast queue that is in FIFO format shares the space in the internal memory block. The size and starting address can also be programmed through memory configuration command. ZL50404 28 Zarlink Semiconductor Inc. Data Sheet ...

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... Basic Flow Shortly after a frame enters the ZL50404 and is written to the Frame Data Buffer (FDB), the frame engine generates a Switch Request, which is sent to the search engine. The switch request consists of the first 64 bytes of the frame, which contain all the necessary information for the search engine to perform its task. When the search engine is done, it writes to the Switch Response Queue, and the frame engine uses the information provided in that queue for scheduling and forwarding ...

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... This feature filters unnecessary traffic, thereby providing intelligent control over traffic flows and broadcast traffic. MAC address filtering allows the ZL50404 to block an incoming packet to an interface when it sees a specified MAC address in either the source address or destination address of the incoming packet. For example, if your network is congested because of high utilization from a MAC address, you can filter all traffic transmitted from that address and restore network flow, while you troubleshoot the problem ...

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... Extensive core QoS mechanisms are built into the ZL50404 architecture to ensure policy enforcement and buffering of the ingress port, as well as weighted fair-queue (WFQ) scheduling at the egress port. In the ZL50404, QoS-based policies sort traffic into a small number of classes and mark the packets accordingly. The QoS identifier provides specific treatment to traffic in different classes, so that different quality of service is provided to each class ...

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... Definition” on page 52). For example, ports 1-3 might be assigned to the Marketing VLAN, ports 4-6 to the Engineering VLAN, and ports 7-9 to the Administrative VLAN. The ZL50404 determines the VLAN membership of each packet by noting the port on which it arrives. From there, the ZL50404 determines which outgoing port(s) is/are eligible to transmit each packet, or whether the packet should be discarded. ...

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... The TxDMA will pull frame data from the memory and forward it granule-by-granule to the MAC TxFIFO of the destination port. 6.2 Frame Engine Details This section briefly describes the functions of each of the modules of the ZL50404 frame engine. 6.2.1 FCB Manager The FCB manager allocates FCB handles to incoming frames, and releases FCB handles upon frame departure. ...

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... Table 7 shows examples of QoS applications with three transmission priorities, but best effort (P0) traffic may form a fourth class with no bandwidth or latency assurances. MMAC port actually has four total transmission priorities. ZL50404 34 Zarlink Semiconductor Inc. ...

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... It is also possible to add a fourth class that has strict priority over the other three; if this class has even one frame to transmit, then it goes first. In the ZL50404, each RMAC port will support two total classes, and the MMAC port will support four classes. We will discuss the various modes of scheduling these classes in the next section ...

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... Although traffic shaping is not a primary function of the ZL50404, the chip does implement a shaper for every queue in the MMAC port. Our goal in shaping is to control the average rate of traffic exiting the ZL50404. If shaper is enabled, strict priority will be applied to that queue. The priority between two shaped queue is the same as in strict priority scheduling ...

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... Though we do have global resource management nothing other than per port WRED to prevent this situation locally. We assume the traffic is policed at a prior stage to the ZL50404 or WRED dropping is fine and shall restrain this situation. ...

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... Such a temporary region is necessary, because when the frame first enters the ZL50404, its destination port and class are as yet unknown, and so the decision to drop or not needs to be temporarily postponed. This ensures that every frame can be received first before subjecting them to the frame drop discipline after classifying ...

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... Xon is triggered when a port is currently being flow controlled, and all of that port’s reserved FDB slots have been released. Note that the ZL50404’s per-source-port FDB reservations assure that a source port that sends a single frame to a congested destination will not be flow controlled. ...

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... On the receiving side, the MAC will also monitor the activity. If there is no good packet received for more than 2X the set period, an alarm will be raised to the CPU. The LHB packet is only used by the ZL50404 to reset the timeout counter ignored otherwise (i.e. not passed on within the system). ...

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... VLAN. When a multicast packet is sent in from port 3, the ZL50404 select port 0,1,2,3,4,5 and 6 as potential destination based on the VLAN. Then port 3 and 4 are removed because they belong to the source port group (trunk group 1). Two ports from trunk group 0 will be removed based on the hash key ...

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... Up to two ports can be setup as mirrored ports result, the traffic (both ingress and egress specific port can be monitored by setting up both mirrored ports. Once a port is setup as mirrored port, it cannot be used for regular traffic. The mirrored port can be any port in the ZL50404. 9.2 Using port mirroring for loop back To perform remote loop back test, port mirroring can be used to bounce back the packet to the source port to check the data path ...

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... Clocks 11.1 Clock Requirements 11.1.1 System Clock (SCLK) speed requirement SCLK is the primary clock for the ZL50404 device. The speed requirement is based on the system configuration. Below is a table for a few configuration. Configuration 1-5 ports 10/100M 11.1.2 RMAC Reference Clock (M_CLK) speed requirement M_CLK MHz clock used for the RMAC ports (ports 0-3). ...

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... Hardware Statistics Counters List ZL50404 hardware provides a full set of statistics counters for each Ethernet port. The CPU accesses these counters through the CPU interface. All hardware counters are rollover counters. When a counter rolls over, the CPU is interrupted, so that long-term statistics may be kept. The MAC detects all statistics, except for the delay exceed discard counter (detected by buffer manager) and the filtering counter (detected by queue manager) ...

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... Late Collision B[29] F-U Notation: X-Y Address in the contain memory X: Size and bits for the counter Y: D Word counter d: 24 bits counter bit [23: bits counter bit [31:24 bits counter bit [23:16] U1: 16 bits counter bit [15: bits counter bit [31:16] u: ZL50404 45 Zarlink Semiconductor Inc. Data Sheet ...

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... No collisions 12.2.1.4 AlignmentErrors Counts number of valid frames received with bad alignment (not byte-aligned). Frame size: No framing error No collisions ZL50404 > 64 bytes, < 1522 bytes if VLAN Tagged; (< 1518 bytes if not VLAN Tagged) > 64 bytes, < 1522 bytes if VLAN Tagged; (< 1518 bytes if not VLAN Tagged) > 64 bytes, < ...

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... Frame size: 12.2.1.9 LateEvents Counts number of collision events that occurred late (after LateEventThreshold = 64 bytes). Frame size: Events are also counted by collision counter ZL50404 > 64 bytes, > 1522 bytes if VLAN Tagged; (> 1518 bytes if not VLAN Tagged) don’t care don’t care < 10 bytes don’ ...

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... InDiscards Counts number of valid frames received which were discarded (i.e., filtered) by the forwarding process. 12.3.1.4 DelayExceededDiscards Counts number of frames discarded due to excessive transmit delay through the bridge. 12.3.1.5 MtuExceededDiscards Counts number of frames discarded due to excessive size. ZL50404 > Jabber 48 Zarlink Semiconductor Inc. Data Sheet ...

Page 49

... Counts number of frames received with FCS or alignment errors Frame size: No collisions: 12.4.1.6 UndersizePkts Counts number of frames received with size less than 64 bytes. Frame size: No FCS error No framing error No collisions ZL50404 > 64 bytes, < 1522 bytes if VLAN Tagged; (< 1518 bytes if not VLAN Tagged) < 64 bytes, 49 Zarlink Semiconductor Inc. Data Sheet ...

Page 50

... Pkts256to511Octets for any packet with size from 256 bytes to 511 bytes Pkts512to1023Octets for any packet with size from 512 bytes to 1023 bytes ZL50404 > 1522 bytes if VLAN Tagged; (> 1518 bytes if not VLAN Tagged) don’t care don’t care < ...

Page 51

... Miscellaneous Counters In addition to the statistics groups defined in previous sections, the ZL50404 has other statistics counters for its own purposes. We have two counters for flow control – one counting the number of flow control frames received, and another counting the number of flow control frames sent. We also have two counters, one for unicast frames sent, and one for non-unicast frames sent. A broadcast or multicast frame qualifies as non-unicast. Furthermore, we have a counter called “ ...

Page 52

... Register Definition 13.1 ZL50404 Register Description Register 0. ETHERNET Port Control Registers (Substitute [n] with Port number (0..3,8,9)) ECR1Pn Port Control Register 1 for Port n ECR2Pn Port Control Register 2 for Port n ECR3Pn Port Control Register 3 for Port n ECR4Pn Port Control Register 4 for Port n BUF_LIMIT Frame Buffer Limit ...

Page 53

... Low AGETIME_HIGH MAC Address Aging Time High SE_OPMODE Search Engine Operating Mode 5. Global QOS Control QOSC QOS Control UCC Unicast Congestion Control Table 12 - Register Description (continued) ZL50404 CPU Addr Description (Hex) 229+2n 300 301 302 303 304 305 306 310+n 323 ...

Page 54

... Priority WLPP76 Well Known Logic Port 6 and 7 Priority WLPE Well Known Logic Port Enable WLPFD Well Known Logic Port Force Discard Enable Table 12 - Register Description (continued) ZL50404 CPU Addr Description (Hex) 511 512 513 514 515 518 519 ...

Page 55

... MII Command Register 1 MIIC2 MII Command Register 2 MIIC3 MII Command Register 3 MIID0 MII Data Register 0 MIID1 MII Data Register 1 USD One micro second divider Table 12 - Register Description (continued) ZL50404 CPU Addr Description (Hex) 570+2n 571+2n 590 591 592 593 594 595 ...

Page 56

... Address 5 MIRROR_SRC_MAC0 Mirror Source MAC Address 0 MIRROR_SRC_MAC1 Mirror Source MAC Address 1 MIRROR_SRC_MAC2 Mirror Source MAC Address 2 MIRROR_SRC_MAC3 Mirror Source MAC Address 3 Table 12 - Register Description (continued) ZL50404 CPU Addr Description (Hex) 60A 60B 610 611 612 613 614 620 621 622 700 ...

Page 57

... E. System Diagnostic DTSRL Test Register Low DTSRM Test Register Medium TESTOUT0 Testmux Output [7:0] TESTOUT1 Testmux Output [15:8] MASK0 MASK Timeout 0 MASK1 MASK Timeout 1 Table 12 - Register Description (continued) ZL50404 CPU Addr Description (Hex) 70A 70B 70C 710 711 800+n 820+n 840+n 848 849 ...

Page 58

... FCB_TAIL_PTR1 FCB Tail Pointer [15:8] FCB_NUM0 FCB Number [7:0] FCB_NUM1 FCB Init Start and FCB Number [14:8] BM_RLSFF_CTRL Read control register BM_RLSFF_INFO0 Bm_rlsfifo_info[7:0] BM_RLSFF_INFO1 Bm_rlsfifo_info[15:8] Table 12 - Register Description (continued) ZL50404 CPU Addr Description (Hex) E12 E13 E14 E80-E82 E90+n EA0+n EA8 EA9 EAA EAB ...

Page 59

... Global Control Register DCR Device Control Register DCR1 Device Control Register 1 DPST Device Port Status Register DTST Data read back register DA DA Register Table 12 - Register Description (continued) ZL50404 CPU Addr Description (Hex) ECA ECB ECC ECD F00 F01 F02 F03 F04 ...

Page 60

... Set this bit to indicate that the following Write to the Receive FIFO is the last one (EOF). This bit will be self-cleared. Bit [5]: Set this bit to re-start the data that is sent from the CPU to Receive FIFO (re-align). This feature can be used for software debug. For normal operation must be '0'. Bit [7:6]: Reserved. Must be '0' ZL50404 60 Zarlink Semiconductor Inc. Data Sheet ...

Page 61

... Data is read from the Control Command Frame Transmit Buffer1 13.2.7 Control Command Frame Buffer2 Access Register • CPU receive control frames (16 bits) • Address = 7 (read only) • When CPU reads this register: Data is read from the Control Command Frame Transmit Buffer2 ZL50404 61 Zarlink Semiconductor Inc. Data Sheet ...

Page 62

... Bit [7: Spanning tree state (IEEE 802.1D spanning tree protocol Blocking Listening Learning Forwarding: ZL50404 Frame is dropped Frame is dropped Frame is dropped. Source MAC address is learned. Frame is forwarded. Source MAC address is learned. (Default) 62 Zarlink Semiconductor Inc. ...

Page 63

... Bit [5:4] Reserved, Must be 0. Bit [7:6] Security Enable. The ZL50404 checks the incoming data for one of the following conditions: • If the source MAC address of the incoming packet is in the MAC table and is defined as secure address but the ingress port is not the same as the port associated with the MAC address in the MAC table. • ...

Page 64

... In this mode, the packet is looped back in the MAC layer before going out of the chip. You must force linkup at full duplex as well. External loopback is another level of system diagnostic which involves the PHY device to loopback the packet. Bit [4:3]: Interface mode GPSI mode 01 - MII mode 10 - Reserved 11 - RMII mode (Default) ZL50404 64 Zarlink Semiconductor Inc. Data Sheet ...

Page 65

... Reserved Bit [1]: Enable RXCLK output. Active high 0: Disable (Default) 1: M9_RXCLK pin becomes output in MII mode Note: To configure port 9 with the device providing the interface clocks, you need to tie M9_RXCLK to M9_MTXCLK externally as M9_MTXCLK is not a bidirectional clock. ZL50404 65 Zarlink Semiconductor Inc. Data Sheet ...

Page 66

... CPU Address:h036 Accessed by CPU (R/W) Bit [6:0]: Frame Buffer Limit (max 4 KB). Multiple of 64 bytes (Default 0x40) Bit [7]: Reserved 13.3.1.6 FCC – Flow Control Grant Period CPU Address:h037 Accessed by CPU (R/W) Bit [2:0]: Flow Control Grant Period (Default 0x3) Bit [7:3]: Reserved ZL50404 66 Zarlink Semiconductor Inc. Data Sheet ...

Page 67

... PVMAP00_3 – Port 0 Configuration Register 3 I²C Address h3E, CPU Address:h105 Accessed by CPU and I²C (R/W) Bit [2:0]: Reserved Bit [5:3]: Default Transmit priority. Used when Bit [7]=1 (Default 0) Transmit Priority Level 0 (Lowest) Transmit Priority Level 1 Transmit Priority Level 2 Transmit Priority Level 3 (Highest) ZL50404 67 Zarlink Semiconductor Inc. Data Sheet ...

Page 68

... Support MAC address 0 0: MAC address 0 is not learned. (Default) 1: MAC address 0 is learned. Bit [5]: Disable IEEE multicast control frame (0180C2000000 to 0180C20000FF) to CPU in managed mode. 0: Packet is forwarded to CPU (Default) 1: Packet is forwarded as multicast Bit [6]: Reserved. Must be 0. ZL50404 68 Zarlink Semiconductor Inc. Data Sheet ...

Page 69

... Hash result 1 destination port number (Default 0) 13.3.3.3 TRUNKn_HASH32 – Trunk group 0~7 hash result 3/2 destination port number CPU Address:h209+ trunk group) Accessed by CPU (R/W) Bit [3:0] Hash result 2 destination port number (Default 0) Bit [7:4] Hash result 3 destination port number (Default 0) ZL50404 TRUNK0 ...

Page 70

... Ports belonging to the same trunk group should only have a single port set to “1” per entry. The port set to “1” is picked to transmit the multicast frame when the hash value is met. Hash Value =0 Hash Value =1 Hash Value =2 Hash Value =3 Hash Value =4 Hash Value =5 Hash Value =6 Hash Value =7 ZL50404 HASH0-1 HASH0-0 HASH1-1 HASH1-0 HASH2-1 HASH2-0 HASH3-1 HASH3-0 HASH4-1 ...

Page 71

... MAC5 to MAC0 registers form the CPU MAC address. When a packet with destination MAC address match MAC [5:0], the packet is forwarded to the CPU. 13.3.4.1 MAC0 – CPU MAC address byte 0 CPU Address:h300 Accessed by CPU (R/W) Bit [7:0]: Byte 0 of the CPU MAC address (Default 0) ZL50404 MAC3 MAC2 MAC1 MAC0 71 Zarlink Semiconductor Inc. Data Sheet ...

Page 72

... The CPU can dynamically mask the interrupt when it is busy and doesn’t want to be interrupted. (Default 0x00 Mask the interrupt - 0: Unmask the interrupt (Enable interrupt) Bit [0]: CPU frame interrupt. CPU frame buffer has data for CPU to read Bit [1]: Control Command 1 interrupt. Control Command Frame buffer1 has data for CPU to read ZL50404 72 Zarlink Semiconductor Inc. Data Sheet ...

Page 73

... INTP_MASK4 CPU Address:h314 (Port CPU,MMAC) 13.3.4.10 RQS – Receive Queue Select CPU Address:h323 Accessed by CPU (RW) Select which receive queue is used. Bit [0]: Select Queue 0 Bit [1]: Select Queue 1 Bit [2]: Select Queue 2 Bit [3]: Select Queue 3 Bit [4]: Select Multicast Queue 0 Bit [5]: Select Multicast Queue 1 ZL50404 73 Zarlink Semiconductor Inc. Data Sheet ...

Page 74

... MAC23 – Increment MAC port 2,3 address CPU Address:h326 Accessed by CPU (RW) Bit [2:0]: Bit [42:40] of Port 2 MAC address Bit [3]: Reserved Bit [6:4]: Bit [42:40] of Port 3 MAC address Bit [7]: Reserved 13.3.4.14 MAC9 – Increment MAC port 9 address CPU Address:h329 Accessed by CPU (RW) Bit [7:0]: Bit [47:40] of Port 9 MAC address ZL50404 74 Zarlink Semiconductor Inc. Data Sheet ...

Page 75

... CPU command queue status The command is under processing. Bit [0]: Insertion Fail (May be due to queue full, WRED or filtering) Bit [1]: 13.3.4.17 CPUGRNHDL0 - CPUGRNHDL1 – CPU Allocated Granule Pointer CPU Address:h338-339 Accessed by CPU, (RO) 15 CG1 CG0 ZL50404 CQ3 CQ2 CQ1 0 75 Zarlink Semiconductor Inc. Data Sheet 0 CQ0 ...

Page 76

... AGETIME_LOW – MAC address aging time Low I²C Address h049; CPU Address:h400 Accessed by CPU and I²C (R/W) Used in conjuction with AGETIME_HIGH. The ZL50404 removes the MAC address from the data base and sends a Delete MAC Address Control Command to the CPU. Bit [7:0]: ...

Page 77

... Disable speed-up aging when MCT resource is low. 0 – Enable speed-up aging when MCT resource is low. (Default) Bit [7]: Slow Learning 1– Enable slow learning. Learning is temporary disabled when search demand is high 0 – Learning is performed independent of search demand (Default) ZL50404 77 Zarlink Semiconductor Inc. Data Sheet ...

Page 78

... MCC – Multicast Congestion Control I²C Address h069, CPU Address: 511 Accessed by CPU and I²C (R/W) Bit [7:0]: In multiples of 16 granules (granularity). Used for triggering MC flow control when destination port’s multicast best effort queue reaches MCC threshold. (Default 0x6) ZL50404 78 Zarlink Semiconductor Inc. Data Sheet ...

Page 79

... See Programming QoS Registers application note, ZLAN-42, for more information 13.3.6.7 RDRC2 – WRED Rate Control 2 CPU Address 515 Accessed by CPU (R/W) Bits[3:0]: Corresponds to the frame drop percentage RB%, for rate control. Granularity 6.25%. Bits[7:4]: Corresponds to the frame drop percentage RA% for rate control. Granularity 6.25%. ZL50404 79 Zarlink Semiconductor Inc. Data Sheet ...

Page 80

... VLAN priority field. For example, programming a value of 7 into bit 2:0 of the AVPML register would map packet VLAN priority 0 into Internal transmit priority 7. The new priority is used inside the ZL50404. When the packet goes out it carries the original priority. Bit [2:0]: ...

Page 81

... Frame drop priority when VLAN Tag priority field is 4 (Default 0) Bit [5]: Frame drop priority when VLAN Tag priority field is 5 (Default 0) Bit [6]: Frame drop priority when VLAN Tag priority field is 6 (Default 0) Bit [7]: Frame drop priority when VLAN Tag priority field is 7 (Default 0) ZL50404 81 Zarlink Semiconductor Inc. Data Sheet ...

Page 82

... Map TOS into frame discard when low priority buffer usage is above threshold Bit [0]: Frame drop priority when TOS field is 0 (Default 0) Bit [1]: Frame drop priority when TOS field is 1 (Default 0) Bit [2]: Frame drop priority when TOS field is 2 (Default 0) ZL50404 82 Zarlink Semiconductor Inc. Data Sheet ...

Page 83

... Enable Protocol 7 Force Discard User Defined Logical Ports and Well Known Ports The ZL50404 supports classifying packet priority through layer 4 logical port information. It can be setup by 8 Well Known Ports, 8 User Defined Logical Ports, and 1 User Defined Range. The 8 Well Known Ports supported are: • ...

Page 84

... I²C Address h0AA, CPU Address 562 Accessed by CPU and I²C (R/W) Bits[3:0]: Priority setting, transmission + dropping, for Well known port 4 (111 for sun remote procedure call) Bits[7:4]: Priority setting, transmission + dropping, for Well known port 5 (22555 for IP Phone call setup) ZL50404 84 Zarlink Semiconductor Inc. Data Sheet ...

Page 85

... Bits[3]: Enable Well Known Port 3 Force Discard Bits[4]: Enable Well Known Port 4 Force Discard Bits[5]: Enable Well Known Port 5 Force Discard Bits[6]: Enable Well Known Port 6 Force Discard Bits[7]: Enable Well Known Port 7 Force Discard ZL50404 85 Zarlink Semiconductor Inc. Data Sheet ...

Page 86

... USER_PORT_[5:4]_PRIORITY - User Define Logic Port 5 and 4 Priority I²C Address h0A4, CPU Address 592 Accessed by CPU and I²C (R/W) Bits[3:0]: Priority setting, transmission + dropping, for logic port 4 Bits[7:4]: Priority setting, transmission + dropping, for logic port 5 (Default 00) ZL50404 Zarlink Semiconductor Inc. Data Sheet ...

Page 87

... Enable User Port 2 Force Discard Bits[3]: Enable User Port 3 Force Discard Bits[4]: Enable User Port 4 Force Discard Bits[5]: Enable User Port 5 Force Discard Bits[6]: Enable User Port 6 Force Discard Bits[7]: Enable User Port 7 Force Discard ZL50404 87 Zarlink Semiconductor Inc. Data Sheet ...

Page 88

... RLOW and RHIGH form a range for logical ports to be classified with priority specified in RPRIORITY. Bits[0]: Drop Priority (inclusive only) Bit [3:1] Transmit Priority (inclusive only) Bit [5:4] Reserved Bit [7: Filtering 01 - Exclusive Filtering (x<=RLOW or x>=RHIGH Inclusive Filtering (RLOW<x<RHIGH Invalid ZL50404 88 Zarlink Semiconductor Inc. Data Sheet ...

Page 89

... Bit [2]: Support DS EF Code. 0 – Disable (Default) 1 – Enable (all ports) When 101110 is detected in DS field (TOS[7:2]), the frame priority is set for 110 and drop is set for 0. Bit [3]: Reserved. Must be 0. Bit [4]: Reserved. Must be 1. ZL50404 89 Zarlink Semiconductor Inc. Data Sheet ...

Page 90

... Bit [6:5] OP – Operation code “10” for read command and “01” for write command Bit [7] Reserved Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then program MII command. ZL50404 90 Zarlink Semiconductor Inc. Data Sheet ...

Page 91

... M_CLK signal. To compensate for this, this register is required to be programmed. For example. If 20MHz is used on M_CLK, to compensate for the difference, this register is programmed with 20 to provide 1usec for internal reference. Bits[7:6]: Reserved ZL50404 91 Zarlink Semiconductor Inc. Data Sheet ...

Page 92

... FF Σ I²C register = When the ZL50404 boots from the EEPROM the checksum is calculated and the value must be zero. If the checksum is not zeroed the ZL50404 does not start and pin CHECKSUM_OK is set to zero. 13.3.7.13 LHBTimer – Link Heart Beat Timeout Timer CPU Address:h610 Accessed by CPU (R/W) In slot time (512 bit time) ...

Page 93

... MIRROR CONTROL – Port Mirror Control Register CPU Address 70C Accessed by CPU (R/W) (Default 00) Bit [3:0]: Destination port to be mirrored to. Bit [4] Mirror Flow from MIRROR_SRC_MAC[5:0] to MIRROR_DEST_MAC[5:0] Bit [5] Mirror Flow from MIRROR_DEST_MAC[5:0] to MIRROR_SRC_MAC[5:0] Bit [6]: Mirror when address is destination Bit [7]: Mirror when address is source ZL50404 93 Zarlink Semiconductor Inc. Data Sheet ...

Page 94

... Mirror enable 13.3.8.5 RMAC_MIRROR1 – RMAC Mirror 1 CPU Address 711 Accessed by CPU (R/W) Bit [2:0]: Source port to be mirrored Bit [3]: Mirror path 0: Receive 1: Transmit Bit [6:4]: Destination port for mirrored traffic Bit [7]: Mirror enable ZL50404 DEST_MAC3 DEST_MAC2 DEST_MAC1 [31:24] [23:16] [15:8] (Default 00) (Default 00) (Default 00) SRC_MAC3 SRC_MAC2 SRC_MAC1 [31:24] [23:16] ...

Page 95

... Flooding Control Register (FCRn). (Default 0) 13.3.9.3 PR100_n – Port 0~3 Reservation I²C Address h06A+n, CPU Address 840 port number) Accessed by CPU and I²C (R/W) Expressed in multiples of 16 granules. (Default 0x6) ZL50404 To turn off the rate limit, program the 95 Zarlink Semiconductor Inc. Data Sheet ...

Page 96

... L1 threshold, received frame will subject to X% (high drop (low drop) WRED. When the queue size exceeds L2 threshold, received frame will either be filtered (high drop) or subject to Z% WRED. 13.3.9.10 QOSC02, QOSC07 - Classes Byte Limit port 1-3 I²C Address 07A-07F, CPU Address:h882-887 Accessed by CPU and I²C (R/W) Same as QOSC00, QOSC01 ZL50404 96 Zarlink Semiconductor Inc. Data Sheet ...

Page 97

... The shaper setting override the NS setting. Bit [5:0]: Class scheduling credit Bit [6]: Shaper enable Bit [7]: Not strict priority apply ZL50404 2 C Address h088, CPU Address 890 Address h089, CPU Address 891 Address h08A, CPU Address 892) 2 ...

Page 98

... TESTOUT0, TESTOUT1 – Testmux Output [7:0], [15:8] CPU Address E02, E03 Accessed by CPU (RO) 13.3.10.4 MASK0-MASK4 – Timeout Reset Mask CPU Address E10-E14 Accessed by CPU (R/W) Disable timeout reset on selected state machine status. See Programming Timeout Reset application note, ZLAN-41, for more information. ZL50404 98 Zarlink Semiconductor Inc. Data Sheet ...

Page 99

... Bit [2]: RXINF NOT idle for 5 sec Bit [3]: PTCTL NOT idle for 5 sec Bit [4]: Reserved Bit [5]: LHB frame detected Bit [6] LHB receiving timeout Bit [7]: ZL50404 15 BT2 BT1 BT0 Bit [6:0]: TSTOUT[6:0] Bit [8:7]: Invert of TSTOUT[8:7] Bit [9]: TSTOUT[11] Bit [10]: TSTOUT[9] Bit [11]: TSTOUT[10] Bit [14:12]: TSTOUT[14:12] Bit [15]: Always 0 ...

Page 100

... L1 WRED level Bit [9]: priority queue 3 reach L2 WRED level Bit [10]: priority 0 MC queue full Bit [11]: priority 1 MC queue full Bit [12]: priority 2 MC queue full Bit [13]: Priority 3 MC queue full Bit [15:14]: Reserved ZL50404 0 PQSTA 100 Zarlink Semiconductor Inc. Data Sheet ...

Page 101

... Priority queue 3 reach L1 WRED level Bit [9]: Priority queue 3 reach L2 WRED level Bit [10]: Priority 0 MC queue full Bit [11]: Priority 1 MC queue full Bit [12]: Priority 2 MC queue full Bit [13]: Priority 3 MC queue full Bit [15:14]: Reserved ZL50404 0 PQSTA 101 Zarlink Semiconductor Inc. Data Sheet ...

Page 102

... CPU Address EB0+n Accessed by CPU (R/W) Bit [0]: Suspend port scheduling (no departure) Bit [1]: Reset queue Bit [4:2]: Reserved Bit [5]: Force out MAC control frame Bit [6]: Force out XOFF flow control frame Bit [7]: Force out XON flow control frame ZL50404 102 Zarlink Semiconductor Inc. Data Sheet ...

Page 103

... MMAC pool 9: shared pool 10: class 1 pool 11: class 2 pool 12: class 3 pool 13: multicast pool 14: cpu pool 15: reserved Bit [4] If this bit is 1, then all the pools are assigned ZL50404 103 Zarlink Semiconductor Inc. Data Sheet ...

Page 104

... Fcb_tail_ptr[14:8]. The tail pointer of free granule link that CPU assigns. Bit [7] Set 1 to write If CPU wants to write again, CPU has to clear bit 15 and then set bit 15. 13.3.10.19 FCB_NUM0, FCB_NUM1 CPU address EC5 Accessed by CPU (R/W) Bit [7:0] Fcb_number[7:0]. The total number of granules that CPU assigns. ZL50404 104 Zarlink Semiconductor Inc. Data Sheet ...

Page 105

... EC9 and EC8). If the FIFO is not empty, CPU can read out the next by setting the bit 0. Read only happens when bit 0 is changing from 13.3.10.21 BM_RSLFF_INFO[5:0] CPU address EC8 Accessed by CPU (RO) Bit [7:0] Rls_head_ptr[7:0]. CPU address EC9 Accessed by CPU (RO) Bit [6:0] Rls_head_ptr[14:8]. Bit [7] Rls_tail_ptr[0] CPU address ECA Accessed by CPU (RO) Bit [7:0] Rls_tail_ptr[8:1] ZL50404 105 Zarlink Semiconductor Inc. Data Sheet ...

Page 106

... Write ‘1’ to store configuration into external EEPROM and reset chip Bit [2]: Start BIST (Default = 0) Write ‘1’ followed by ‘0’ to start the device’s built-in self-test. The result is found in the DCR register. Bit [3]: Soft Reset (Default = 0) Write ‘1’ to reset chip ZL50404 106 Zarlink Semiconductor Inc. Data Sheet ...

Page 107

... Busy reading configuration from I²C 0: Not busy (not reading configuration from I²C) Bit [2]: 1: BIST in progress 0: BIST not running Bit [3]: 1: RAM Error 0: RAM OK Bit [5:4]: Device Signature 10: ZL50404 device Bit [7:6]: Revision 00: Initial Silicon 01: Second Silicon 13.3.11.3 DCR1 - Device Status Register 1 CPU Address: hF02 Accessed by CPU (RO) Bit [6:0] ...

Page 108

... Disable 0: Enable Bit [5] Reserved Bit [6] Reserved Bit [7] Module deleted (for hot swap purpose) 13.3.11.6 DA – DA Register CPU Address: hFFF Accessed by CPU (RO) Always return 8’h DA. Indicate the CPU interface or serial port connection is good. Bit [7:0] Always return DA ZL50404 108 Zarlink Semiconductor Inc. Data Sheet ...

Page 109

... Caution: Stress above those listed may damage the device. Exposure to the Absolute Maximum Ratings for extended periods may affect device reliability. Functionality at or above these limits is not implied. 14.2 DC Electrical Characteristics V = 3.3 V +/- 10 1.8 V +/- 5% DD ZL50404 -65°C to +150°C -40°C to +85°C +125°C +2. +3. +1. + ...

Page 110

... OUT C I/O Capacitance I/O Thermal resistance with 0 air flow θ ja θ Thermal resistance with 1 m/s air flow ja Thermal resistance with 2 m/s air flow θ ja Thermal resistance between junction and case θ jc ZL50404 Min. 2.4 2.0 < < OUT CC 110 Zarlink Semiconductor Inc. Data Sheet Typ. Max. ...

Page 111

... R1 Bootstrap Pins Outputs Figure 10 - Typical Reset & Bootstrap Timing Diagram Symbol Parameter R1 Delay until RESETOUT# is tri-stated R2 Bootstrap stabilization R3 RESETOUT# assertion ZL50404 Tri-Stated R3 Inputs R2 Min. Typ RESETOUT# state is then determined by the external pull-up/down resistor 1 µs 10 µs Bootstrap pins sampled on rising edge of ...

Page 112

... M[3:0]_RXD[1:0] Input Setup Time M3 M[3:0]_RXD[1:0] Input Hold Time M4 M[3:0]_CRS_DV Input Setup Time M5 M[3:0]_CRS_DV Input Hold Time M6 M[3:0]_TXEN Output Delay Time M7 M[3:0]_TXD[1:0] Output Delay Time Table Characteristics – Reduced Media Independent Interface ZL50404 M_CLK M6-max M6-min Mn_TXEN M7-max M7-min Mn_TXD[1:0] M_CLK M2 Mn_RXD M3 ...

Page 113

... Mn_RXD[3:0] Input Hold Time MM4 M[9,3:0]_CRS_DV Input Setup Time MM5 Mn_CRS_DV Input Hold Time MM6 Mn_TXEN Output Delay Time MM7 Mn_TXD[3:0] Output Delay Time Table Characteristics –Media Independent Interface ZL50404 Mn_TXCLK MM6-max MM6-min Mn_TXEN MM7-max MM7-min Mn _TXD[3:0] Mn_RXCLK MM2 Mn_RXD[3:0] ...

Page 114

... M[3:0]_RXD Input Hold Time SM4 M[3:0]_CRS_DV Input Setup Time SM5 M[3:0]_CRS_DV Input Hold Time SM6 M[3:0]_TXEN Output Delay Time SM7 M[3:0]_TXD Output Delay Time Table Characteristics –General Purpose Serial Interface ZL50404 Mn_ TXCLK SM6-max SM6-min Mn_TXEN SM7-max SM7-min Mn_TXD Mn_RXCLK SM2 ...

Page 115

... MDIO Input Setup and Hold Timing Figure 17 - MDIO Input Setup and Hold Timing Symbol Parameter D1 MDIO input setup time D2 MDIO input hold time D3 MDIO output delay time ZL50404 MDC D1 D2 MDIO MDC D3-max D3-min MDIO Figure 18 - MDIO Output Delay Timing MDC=500 KHz Min ...

Page 116

... I²C Input Setup Timing Symbol Parameter S1 SDA input setup time S2 SDA input hold time S3* SDA output delay time * Open Drain Output. Low to High transistor is controlled by external pullup resistor. ZL50404 SCL S2 S1 SDA Figure 19 - I²C Input Setup Timing SCL S3-max S3-min SDA Figure 20 - I² ...

Page 117

... Dataout Figure 22 - Serial Interface Output Delay Timing Symbol Parameter D1 DATAIN setup time D2 DATAIN hold time D3 DATAOUT output delay time D4 STROBE low time D5 STROBE high time ZL50404 Figure 21 - Serial Interface Setup Timing D3-max D3-min Min. (ns µ µ µ ...

Page 118

... Symbol Parameter TCK frequency of operation TCK cycle time TCK clock pulse width TRST# assert time J1 TMS, TDI data setup time J2 TMS, TDI data hold time J3 TCK to TDO data valid ZL50404 J1 J2 Figure 23 - JTAG Timing Diagram Min. Typ. Max ...

Page 119

... INT_MASK and INTP_MASK registers should state that the default register value is 0x00 15.4 August 2004 • Added Errata List to document • Added section on SCL clock generation • Interrupt Register was incorrectly identified as read only, should be read/write • Clarified that only bit [7] is not self-clearing ZL50404 119 Zarlink Semiconductor Inc. Data Sheet ...

Page 120

... TOP VIEW SIDE VIEW c Zarlink Semiconductor 2002 All rights reserved. 1 ISSUE 213730 ACN 14Nov02 DATE APPRD. BOTTOM VIEW b Previous package codes Dimension MIN MAX 1. 0.30 0.50 0.53 REF A2 D 16.90 17.10 E 16.90 17.10 b 0.40 0.60 e 1.00 N 208 Conforms to JEDEC MO-192 Package Code ...

Page 121

... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...