zl50404 Zarlink Semiconductor, zl50404 Datasheet - Page 22

• Manufacturer Part Number: zl50404
• Description: Lightly Managed/unmanaged 5-port 10/100m Ethernet Switch
• Manufacturer: Zarlink Semiconductor

2.6
The ZL50404 provides the ability to monitor a link and detect a simple link failure. The Link Heart Beat (LHB) packet
generation module allows simultaneous tracking of all the RMAC ports.
Periodically, a LHB message will be sent for each link when inactivity is detected with in a programmable time
period, If a reply is not received in a specified amount of time, the failover detection module will identify a
point-to-point failure for that link. The failover detection module will then interrupt the CPU.
The LHB packet response module can also reply to LHB messages initiated by other ZL50404 devices in the
system, or by non-ZL50404 devices which use a conventional and recognizable LHB message format.
2.7
The ZL50404 supports a state machine monitoring block which can trigger a reset or interrupt if any state machine
is determined to be stuck in a non-idle state for more than 5 seconds. This feature is enabled via a bootstrap pin
(TSTOUT12). It also requires some register configuration via the CPU interface.
See Programming Timeout Reset application note, ZLAN-41, for more information.
2.8
An IEEE1149.1 compliant test interface is provided for boundary scan.
3.0
One extra port is dedicated to the CPU via the CPU interface module. Two modes this port can operate: lightly
managed or unmanaged mode. The different between these modes is tx/rx Ethernet frame, tx/rx control frame and
receiving interrupt due to the lack of constant attention or processing power from the CPU.
Supported CPU interface modes are
1. Lightly Managed Serial. Configuration registers access, Control frame and CPU transmit/receive packets are
2. Unmanaged Serial. The device can be configured by EEPROM using an I²C interface at bootup, or via a syn-
The CPU interface provides for easy and effective management of the switching system.
Figure 3 on page 23 provides an overview of the SSI interface.
Lightly Managed Serial
Unmanaged Serial
sent through a synchronous serial interface (SSI) bus.
chronous serial interface (SSI) otherwise. All configuration registers and internal control blocks are accessible
by the interface. However, the CPU cannot receive or transmit frames nor will it receive any interrupt informa-
tion.
Heartbeat Packet Generation and Response
Timeout Reset Monitor
JTAG
Management and Configuration
Operation Mode
Table 5 - Supported CPU interface modes
NA
NA
ISA Interface
Zarlink Semiconductor Inc.
ZL50404
22
Yes
Yes
Serial
No
No
MII
No
Yes
Data Sheet
I²C