zl50404 Zarlink Semiconductor, zl50404 Datasheet - Page 108

• Manufacturer Part Number: zl50404
• Description: Lightly Managed/unmanaged 5-port 10/100m Ethernet Switch
• Manufacturer: Zarlink Semiconductor

13.3.11.4
CPU Address:hF03
Accessed by CPU (R/W)
13.3.11.5
CPU Address: hF04
Accessed by CPU (RO)
This register provides various internal information as selected in DPST bit [4:0]. Refer to the PHY Port Control
Application Note, ZLAN-37.
13.3.11.6
CPU Address: hFFF
Accessed by CPU (RO)
Always return 8’h DA. Indicate the CPU interface or serial port connection is good.
Bit [4:0]:
Bit [7:5]:
Bit [0]
Bit [1]
Bit [2]
Bit [3]
Bit [4]
Bit [5]
Bit [6]
Bit [7]
Bit [7:0]
DPST – Device Port Status Register
DTST – Data read back register
DA – DA Register
Read back index register. This is used for selecting what to read back from
DTST. (Default 00)
Reserved
Flow control enable
Full duplex port
Fast Ethernet port
Link is down
Auto negotiation enabled
1: Disable
0: Enable
Reserved
Reserved
Module deleted (for hot swap purpose)
Always return DA
-
-
-
-
-
-
-
5’b00000 - Port 0 Operating mode and Negotiation status
5’b00001 - Port 1 Operating mode and Negotiation status
5’b00010 - Port 2 Operating mode and Negotiation status
5’b00011 - Port 3 Operating mode and Negotiation status
5’b001xx - Reserved
5’b01000 - Port CPU Operating mode and Negotiation status
5’b01001 - Port MMAC Operating mode and Negotiation status
Zarlink Semiconductor Inc.
ZL50404
108
Data Sheet