zl50404 Zarlink Semiconductor, zl50404 Datasheet - Page 43

• Manufacturer Part Number: zl50404
• Description: Lightly Managed/unmanaged 5-port 10/100m Ethernet Switch
• Manufacturer: Zarlink Semiconductor

11.0
11.1
11.1.1
SCLK is the primary clock for the ZL50404 device. The speed requirement is based on the system configuration.
Below is a table for a few configuration.
11.1.2
M_CLK is a 50 MHz clock used for the RMAC ports (ports 0-3).
If none of the RMAC ports are configured in RMII mode or Reverse MII mode, a different clock frequency can be
applied to M_CLK, as long as it's less than 50 MHz. In this case, register USD must be set to provide an internal
1usec timing.
11.1.3
REF_CLK is a reference clock required for the MMAC port (port 9).
If the device is in a 9 port 10/100 configuration only, REF_CLK can be a lower frequency clock and can be
connected to M_CLK to reduce the number of clock sources.
If port 9 is not being used, REF_CLK can be left unconnected.
11.1.4
TCK is a clock used for the JTAG port. The frequency on this clock can vary. Refer to “JTAG (IEEE 1149.1-2001)”
on page 118 for the frequency range.
11.2
11.2.1
MDC is used for the MII Management Interface and clocks data on MDIO. It is generated by the device from
M_CLK and is equal to 500 kHz (M_CLK/100). If a different speed clock other than 50MHz is used on M_CLK, the
USD register must be programmed to reset MDC.
11.2.2
SCL is used for the I2C interface and clocks data on SDA. It is generated by the device from M_CLK and is equal
to 50kHz (M_CLK/1000). If a different speed clock other than 50MHz is used on M_CLK, the USD register must be
programmed to reset SCL.
11.2.3
If the RMAC ports are configured in Reverse MII mode, TXCLK and RXCLK are generated from M_CLK and are
equal to M_CLK/2 for 100M mode or M_CLK/20 for 10M mode. M_CLK needs to be a 50 MHz clock in this mode.
1-5 ports 10/100M
Clock Requirements
Clock Generation
Clocks
System Clock (SCLK) speed requirement
RMAC Reference Clock (M_CLK) speed requirement
MMAC Reference Clock (REF_CLK) speed requirement
JTAG Test Clock (TCK) speed requirements
MDC
SCL
Ethernet Interface Clocks
Configuration
Table 11 - SCLK Speed Requirements
Zarlink Semiconductor Inc.
ZL50404
43
25 Mhz
Minimum SCLK speed
required
Data Sheet