MT48H8M32LFB5-10:G Micron Technology Inc, MT48H8M32LFB5-10:G Datasheet - Page 9

• Manufacturer Part Number: MT48H8M32LFB5-10:G
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M32LFB5-10:G

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/8/7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 65mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

A3–A8 when the burst length is set to eight. The
remaining (least significant) address bit(s) is (are) used
to select the starting location within the block. Full-
page bursts wrap within the page if the boundary is
reached.
Burst Type
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 4.
pdf: 09005aef80d460f2, source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. D 9/04 EN
to ensure compatibility
with future devices.
Accesses within a given burst may be programmed
The ordering of accesses within a burst is deter-
*Should program
Figure 3: Mode Register Definition
0
13
M13
BA1
M10 = “0, 0”
0
12
M12
BA0
Reserved* WB
11
M11
A11
10
M10
A10
M9
0
1
9
M9
A9
Op Mode
M8
8
A8
7
M7 M6
A7 A6
Programmed Burst Length
M8
0
-
Single Location Access
CAS Latency
6
Write Burst Mode
5
M5
A5
M7
0
-
4
M4
A4
M3
BT
M6-M0
Defined
0
1
3
M3
A3
-
M6
M2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Burst Length
2
M2
M1
M5
A2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
M0
M4
1
Operating Mode
Standard Operation
All other states reserved
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
M1
A1
0
M0
A0
Reserved
Reserved
Reserved
Full Page
M3 = 0
Burst Type
Interleaved
Sequential
1
2
4
8
Mode Register (Mx)
Address Bus
Burst Length
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
1
2
3
Reserved
Reserved
Reserved
Reserved
M3 = 1
1
2
4
8
9
Table 5:
NOTE:
LENGTH
Page (y)
1. For full-page accesses: y = 512.
2. For a burst length of two, A1
3. For a burst length of four, A2
4. For a burst length of eight, A3
5. For a full-page burst, the full row is selected and A0
6. Whenever a boundary of the block is reached within a
7. For a burst length of one, A0
BURST
Full
two burst; A0 selects the starting column within the
block.
four burst; A0-A1 select the starting column within the
block.
eight burst; A0-A2 select the starting column within
the block.
A8 select the starting column.
given sequence above, the following access wraps
within the block.
umn to be accessed, and mode register bit M3 is
ignored.
2
4
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
A2
n = A0-A11/
STARTING
ADDRESS
0
0
0
0
1
1
1
1
COLUMN
(location
0-y)
Burst Definition Table
9/8
A1 A0
A1 A0
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Cn + 3, Cn + 4...
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
ORDER OF ACCESSES WITHIN
SEQUENTIAL
Cn, Cn + 1,
…Cn - 1,
MOBILE SDRAM
TYPE =
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
Cn + 2
Cn…
©2003 Micron Technology, Inc. All rights reserved.
0-1
1-0
–
–
–
A8 select the unique col-
A8 select the block-of-
–
A8 select the block-of-
A8 select the block-of-
256Mb: x32
A BURST
PRELIMINARY
INTERLEAVED
Not Supported
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
TYPE =
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0
–