MT48H8M32LFB5-10:G Micron Technology Inc, MT48H8M32LFB5-10:G Datasheet
MT48H8M32LFB5-10:G
Specifications of MT48H8M32LFB5-10:G
Related parts for MT48H8M32LFB5-10:G
MT48H8M32LFB5-10:G Summary of contents
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... Commercial (0° to +70°C) Industrial (-40°C to +85°C) pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_1.fm - Rev. D 9/04 EN ‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS. ...
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... WRITE with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Data Sheet Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32TOC.fm - Rev. D 9/04 EN MOBILE SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 2 ©2003 Micron Technology, Inc. All rights reserved. PRELIMINARY ...
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... List of Figures Figure 1: Pin Assignment (Top View) 90-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Figure 2: Functional Block Diagram 8 Meg x 32 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Figure 3: Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Figure 4: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Figure 5: Low Power Extended Mode Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Figure 6: Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Figure 7: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK< .15 Figure 8: READ Command ...
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... Specifications and Conditions – H Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 DD Table 19 Self Refresh Current Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 DD Table 20: Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32LOT.fm - Rev. D 9/04 EN MOBILE SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 ©2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb: x32 ...
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... MT48H8M32LFF5-10 1.8V/1.8V MT48H8M32LFB5-8 1.8V/1.8V 1.8V/1.8V MT48H8M32LFB5-10 FBGA Part Number System Due to space limitations, FBGA-packaged compo- nents have an abbreviated part marking that is differ- ent from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on the Micron web site, www ...
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... Figure 2: Functional Block Diagram 8 Meg x 32 SDRAM CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH MODE REGISTER COUNTER 12 12 A0-A11, ADDRESS 14 BA0, BA1 REGISTER pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev ROW- BANK0 12 ROW- ADDRESS ADDRESS MUX 4096 LATCH & ...
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... SDRAM x32_2.fm - Rev. D 9/04 EN TYPE Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. ...
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... CLK). Each of the 67,108,864-bit banks is orga- nized as 4,096 rows by 512 columns by 32 bits. Read and write accesses to the SDRAM are burst ori- ented; accesses start at a selected location and con- tinue for a programmed number of locations in a programmed sequence ...
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... M10 = “0, 0” ensure compatibility with future devices M6- Defined - - - M9 Write Burst Mode 0 Programmed Burst Length 1 Single Location Access pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev. D 9/04 EN Table 5: BURST LENGTH 2 4 Address Bus Mode Register (Mx) Burst Length Burst Length ...
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... Low Power pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev. D 9/04 EN MOBILE SDRAM features. The extended mode will default with the tem- perature sensor enabled, full drive strength, and full array refresh ...
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... Only during extreme temperatures would the controller have to select the Address Bus maximum TCSR level. This would guarantee data dur- ing SELF REFRESH. Every cell in the DRAM requires refreshing due Low Power the capacitor losing its charge over time. The refresh 2 1 ...
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... Operation (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD mode register The mode register is loaded via inputs A0, BA0, BA1. ...
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... LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev. D 9/04 EN PRECHARGE The PRECHARGE command is used to deactivate t MRD is met. ...
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... SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW) ...
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... Operation Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Figure 6). After opening a row (issuing an ACTIVE command), ...
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... DISABLE AUTO PRECHARGE BA0,BA1 ADDRESS pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev. D 9/04 EN Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and con- tinue ...
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... ADDRESS DQ NOTE: Each READ command may be to either bank. DQM is LOW. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev. D 9/04 EN ated on any clock cycle following a previous READ command. Full-speed random read accesses can be performed to the same bank, as shown in Figure 11, or each subsequent READ may be performed to a differ- ent bank ...
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... CLK COMMAND ADDRESS DQ CLK COMMAND ADDRESS DQ CLK COMMAND ADDRESS DQ NOTE: Each READ command may be to either bank. DQM is LOW. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev. D 9/04 EN Figure 11: Random READ Accesses READ READ READ READ BANK, BANK, BANK, BANK, COL n ...
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... I/O contention can be avoided given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at least a single- cycle delay should occur between the last read data and the WRITE command. ...
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... CLK COMMAND ADDRESS DQ CLK COMMAND ADDRESS DQ CLK COMMAND ADDRESS DQ NOTE: DQM is LOW. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev. D 9/04 EN Figure 14: READ to PRECHARGE READ NOP NOP NOP PRECHARGE cycles BANK BANK all) COL OUT OUT OUT OUT CAS Latency = 1 T0 ...
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... ADDRESS DQ NOTE: DQM is LOW. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev. D 9/04 EN should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 15 for each possible CAS latency; data element the last desired data element of a longer burst ...
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... An example is shown in Figure 18. Data either the last of a burst of two or the last desired of a longer burst. The 256Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A WRITE com- mand can be initiated on any clock cycle following a previous WRITE command ...
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... The WRITE command may be to any bank, and the READ command may be to any bank. DQM is LOW. CAS latency = 2 for illustration. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev addition, when truncating a WRITE burst, the DQM signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the PRECHARGE command ...
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... CS# and WE# held low with RAS# and CAS# high at the rising edge of the clock, while CKE is low. CKE must be held low during Deep Power Down. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev. D 9/04 EN Figure 22: Terminating a WRITE Burst T0 CLK COMMAND ...
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... CAS latency later. The precharge to bank n will begin when the READ to bank m is registered (Figure 27). pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev. D 9/04 EN MOBILE SDRAM 2. Interrupted by a WRITE (with or without auto pre- charge): A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to pre- vent bus contention ...
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... States BANK m ADDRESS NOTE: DQM is LOW. Figure 28: READ With Auto Precharge Interrupted by a WRITE COMMAND BANK n Internal States BANK m ADDRESS NOTE: 1. DQM is HIGH prevent D pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev CLK READ - AP READ - AP NOP NOP NOP BANK n BANK m ...
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... ADDRESS NOTE: 1. DQM is LOW. Figure 30: WRITE With Auto Precharge Interrupted by a WRITE COMMAND BANK n Internal States BANK m ADDRESS NOTE: 1. DQM is LOW. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev Interrupted by a WRITE (with or without auto pre CLK WRITE - AP READ - AP NOP ...
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... After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge Deep Power-Down is power savings feature of this Mobile SDRAM device. This command is BURST TERMINATE when CKE is high and DEEP POWER DOWN when CKE is low. ...
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... RP has been met. Once 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev COMMAND INHIBIT (NOP/Continue previous operation OPERATION (NOP/Continue previous operation) ...
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... Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when t been met. Once MRD is met, the SDRAM will be in the all banks idle state. Precharging All: Starts with registration of a PRECHARGE ALL command and ends when all banks will be in the idle state. ...
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... A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev. D 9/04 EN WE# COMMAND (ACTION) X COMMAND INHIBIT (NOP/Continue previous operation) ...
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... WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock to the WRITE to bank m. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev begins when the READ to bank m is registered. The last valid WRITE bank Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... V V (All other pins not under test = 0V Output Leakage Current: DQs are disabled; 0V pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev. D 9/04 EN tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating Temperature T A ...
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... Output High Voltage: All inputs: Iout = -4mA Output Low Voltage: All inputs : Iout = 4mA Input Leakage Current: Any input 0V VIN V (All other pins not under test = 0V) DD Output Leakage Current: DQs are disabled; 0V pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev +1.8 ±0.1V +1.8V ±0. SYMBOL ...
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... Refresh period (4,096 rows) AUTO REFRESH period PRECHARGE command period ACTIVE bank a to ACTIVE bank b command Transition time WRITE recovery time Exit SELF REFRESH to ACTIVE command pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev. D 9/04 EN -75 SYMBOL MIN MAX TBD TBD AC (3) ...
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... All banks active; No accesses in progress Operating Current: Burst Mode; Continuous burst; READ or WRITE; All banks active, half DQs toggling every cycle. Auto Refresh Current CKE = HIGH; CS# = HIGH DEEP POWER DOWN pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev. D 9/04 EN SYMBOL t CCD t CKED t ...
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... All banks active; No accesses in progress Operating Current: Burst Mode; Continuous burst; READ or WRITE; All banks active, half DQs toggling every cycle. Auto Refresh Current CKE = HIGH; CS# = HIGH DEEP POWER DOWN pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev +2.5 ±0.2V +2.5 ±0. SYMBOL -75 ...
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... Self Refresh Current: CKE = LOW -- Quarter Bank Refresh Table 20: Capacitance Note: 2; notes appear on page 39 PARAMETER Input Capacitance: CLK Input Capacitance: All other input-only pins Input/Output Capacitance: DQs pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev. D 9/04 EN MAX TEMPERATURE 85ºC 750 750 70º ...
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... V levels 13. I specifications are tested after the device is DD properly initialized. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev 14. Timing actually specified +1.8V fied as a reference only at minimum cycle rate. 15. Timing actually specified by specified as a reference only at minimum cycle rate ...
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... The Load Mode Register for both MR/EMR and 2 Auto Refresh commands can be in any order. However, all must occur prior to an Active command. 5. Device timing is -10 with 100 MHz clock. See Table 14, Electrical Characteristics and Recommended AC Operating Conditions, on page 35. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev ...
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... All banks idle, enter active banks power-down mode NOTE: 1. Violating refresh requirements during power-down may result in a loss of data. See Table 14, Electrical Characteristics and Recommended AC Operating Conditions, on page 35. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev. D 9/04 EN Figure 32: Power-Down Mode CKS ...
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... For this example, the burst length = 2, the CAS latency = 3, and auto precharge is disabled and A11 = “Don’t Care.” See Table 14, Electrical Characteristics and Recommended AC Operating Conditions, on page 35. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev. D 9/04 EN Figure 33: Clock Suspend Mode T2 T3 ...
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... BANK(S) High-Z DQ Precharge all active banks NOTE: 1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands are not required. See Table 14, Electrical Characteristics and Recommended AC Operating Conditions, on page 35. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev. D 9/04 EN Figure 34: Auto Refresh Mode ...
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... BANK(S) High-Z DQ Precharge all active banks NOTE: 1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands are not required. See Table 14, Electrical Characteristics and Recommended AC Operating Conditions, on page 35. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev. D 9/04 EN Figure 35: Self Refresh Mode ...
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... For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE. A9 and A11 = “Don’t Care.” See Table 14, Electrical Characteristics and Recommended AC Operating Conditions, on page 35. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev ...
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... DQ t RCD t RAS t RC NOTE: 1. For this example, the burst length = 4, the CAS latency = and A11 = “Don’t Care.” See Table 14, Electrical Characteristics and Recommended AC Operating Conditions, on page 35. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev READ NOP NOP ...
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... For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE and A11 = “Don’t Care.” 3. PRECHARGE command not allowed or tRAS would be violated. See Table 14, Electrical Characteristics and Recommended AC Operating Conditions, on page 35. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev ...
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... For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE and A11 = “Don’t Care.” 3. PRECHARGE command not allowed or See Table 14, Electrical Characteristics and Recommended AC Operating Conditions, on page 35. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev ...
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... RC - BANK 0 t RRD NOTE: 1. For this example, the burst length = 4, the CAS latency = and A11 = “Don’t Care.” See Table 14, Electrical Characteristics and Recommended AC Operating Conditions, on page 35. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev READ NOP ACTIVE t CMS ...
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... For this example, the CAS latency = and A11 = “Don’t Care.” Page left open; no RP. See Table 14, Electrical Characteristics and Recommended AC Operating Conditions, on page 35. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev. D 9/04 EN Figure 41: Read – Full-page Burst NOP NOP ...
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... BANK DQ t RCD NOTE: 1. For this example, the CAS latency = and A11 = “Don’t Care.” See Table 14, Electrical Characteristics and Recommended AC Operating Conditions, on page 35. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev. D 9/04 EN Figure 42: Read – DQM Operation READ NOP ...
Page 52
... For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE. 2. 15ns is required between <DIN m + 3> and the PRECHARGE command, regardless of frequency and A11 = “Don’t Care.” See Table 14, Electrical Characteristics and Recommended AC Operating Conditions, on page 35. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev ...
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... BANK RCD t RAS t RC NOTE: 1. For this example, the burst length = and A11 = “Don’t Care.” See Table 14, Electrical Characteristics and Recommended AC Operating Conditions, on page 35. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev WRITE NOP NOP NOP t CMH BANK ...
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... For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE. 2. 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency and A11 = “Don’t Care.” 4. PRECHARGE command not allowed else See Table 14, Electrical Characteristics and Recommended AC Operating Conditions, on page 35. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev ...
Page 55
... For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE. 2. 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency and A11 = “Don’t Care.” 4. WRITE command not allowed else See Table 14, Electrical Characteristics and Recommended AC Operating Conditions, on page 35. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev ...
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... RAS - BANK BANK 0 t RRD NOTE: 1. For this example, the burst length = and A11 = “Don’t Care.” See Table 14, Electrical Characteristics and Recommended AC Operating Conditions, on page 35. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev WRITE NOP ACTIVE NOP t CMH ...
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... A9 and A11 = “Don’t Care.” must be satisfied prior to PRECHARGE command Page left open; no RP. See Table 14, Electrical Characteristics and Recommended AC Operating Conditions, on page 35. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev. D 9/04 EN Figure 48: Write – Full-page Burst WRITE NOP NOP ...
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... BANK DQ t RCD NOTE: 1. For this example, the burst length = and A11 = “Don’t Care.” See Table 14, Electrical Characteristics and Recommended AC Operating Conditions, on page 35. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev. D 9/04 EN Figure 49: Write – DQM Operation WRITE NOP ...
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... E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev. D 9/04 EN 6.40 0.80 TYP BALL A1 ID BALL A1 0 ...