MT48H8M32LFB5-10:G Micron Technology Inc, MT48H8M32LFB5-10:G Datasheet - Page 7

• Manufacturer Part Number: MT48H8M32LFB5-10:G
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M32LFB5-10:G

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/8/7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 65mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Table 4:
pdf: 09005aef80d460f2, source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. D 9/04 EN
M7, L8, L2, M3, M2, P1,
R8, N7, R9, N8, P9, M8,
D8, B9, C8, A9, C7, A8,
A2, C3, A1, C2, B1, D2,
N2, R1, N3, R2, E8, D7,
E3, E7, H3, H7, K2, K3
B2, B7, C9, D9, E1, L1,
B8, B3, C1, D1, E9, L9,
G3, H1, H2, J3, G7,H9
G8, G9, F7, G1, G2,
90-BALL VFBGA
M9, N9, P2, P7
M1, N1, P3, P8
K9, K1, F8, F2
A7, F9, L7, R7
A3, F1, L3, R3
J9, K7, K8
D3, E2
J7, H8
J1
J2
J8
Ball Descriptions
RAS#,CAS#,
DQ0–DQ31
SYMBOL
BA0, BA1
DQM0-3
A0–A11
V
WE#
V
CLK
CKE
CS#
V
NC
V
DD
SS
DD
SS
Q
Q
Supply DQ Power: Provide isolated power to DQs for improved noise immunity.
Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
Supply Core Power Supply.
Supply Ground.
TYPE
Input Clock: CLK is driven by the system clock. All SDRAM input signals are
Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Input Chip Select: CS# enables (registered LOW) and disables (registered HIGH)
Input Command Inputs: RAS#, CAS#,and WE# (along with CS#) define the
Input Input/Output Mask: DQM is sampled HIGH and is an input mask signal for
Input Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE,
Input Address Inputs: A0–A11 are sampled during the ACTIVE command (row-
I/O
–
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF
REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in
any bank),DEEP POWER DOWN(all banks idle), or CLOCK SUSPEND
operation (burst/access in progress). CKE is synchronous except after the
device enters power-down and self refresh modes, where CKE becomes
asynchronous until after exiting the same mode. The input buffers,
including CLK, are disabled during power-down and self refresh modes,
providing low standby power.
the command decoder. All commands are masked when CS# is registered
HIGH. CS# provides for external bank selection on systems with multiple
banks. CS# is considered part of the command code.
command being entered.
write accesses and an output enable signal for read accesses. Input data is
masked during a WRITE cycle. The output buffers are placed in a High-Z
state (two-clock latency) when during a READ cycle. DQM0 corresponds to
DQ0-DQ7, DQM1 corresponds to DQ8-DQ15, DQM2 corresponds to DQ16-
DQ23 and DQM3 corresponds to DQ24-DQ31. DQM0-3 are considered
same state when referenced as DQM.
READ, WRITE or PRECHARGE command is being applied. These pins also
provide the op-code during a LOAD MODE REGISTER command
address A0–A11) and READ/WRITE command (column-address A0–A8; with
A10 defining auto precharge) to select one location out of the memory
array in the respective bank. A10 is sampled during a PRECHARGE
command to determine if all banks are to be precharged (A10 HIGH) or
bank selected by BA0, BA1. The address inputs also provide the op-code
during a LOAD MODE REGISTER command.
Data Input/Output: Data bus
Internally Not Connected: These could be left unconnected, but it is
recommended they be connected to Vss. H3 is a no connect for this part
but may be used as A12 in future designs.
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
MOBILE SDRAM
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x32
PRELIMINARY