MT48H8M32LFB5-10:G Micron Technology Inc, MT48H8M32LFB5-10:G Datasheet - Page 29

• Manufacturer Part Number: MT48H8M32LFB5-10:G
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M32LFB5-10:G

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/8/7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 65mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Table 9:
Notes: 1-6; notes appear below table
NOTE:
pdf: 09005aef80d460f2, source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. D 9/04 EN
1. This table applies when CKE
2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are
3. Current state definitions:
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP com-
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must
Write (Auto
Row Active
Read (Auto
CURRENT
Precharge
Precharge
Disabled)
Disabled)
ous state was self refresh).
those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
Idle:The bank has been precharged, and
Row Active: A row in the bank has been activated, and
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been termi-
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been termi-
mands, or allowable commands to the other bank should be issued on any clock edge occurring during these states.
Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to Truth
Table 4.
Precharging: Starts with registration of a PRECHARGE command and ends when
Row Activating: Starts with registration of an ACTIVE command and ends when
Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and
Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and
be applied on each positive clock edge during these states.
STATE
accesses are in progress.
nated.
nated.
bank will be in the idle state.
bank will be in the row active state.
ends when
ends when
Any
Idle
Truth Table – Current State Bank n, Command To Bank n
t
t
CS#
RP has been met. Once
RP has been met. Once
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS# CAS# WE# COMMAND (ACTION)
H
H
H
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
n-1
H
H
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
was HIGH and CKE
H
H
H
H
H
H
X
t
t
L
L
L
L
L
L
L
L
L
L
L
L
RP is met, the bank will be in the idle state.
RP is met, the bank will be in the idle state.
t
RP has been met.
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
ACTIVE (Select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
PRECHARGE
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Truncate READ burst, start PRECHARGE)
BURST TERMINATE
DEEP POWER-DOWN
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
DEEP POWER-DOWN
n
is HIGH (see Truth Table 2) and after tXSR has been met (if the previ-
t
RCD has been met. No data bursts/accesses and no register
29
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
t
RCD is met. Once
RP is met. Once
MOBILE SDRAM
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x32
t
RP is met, the
t
RCD is met, the
PRELIMINARY
NOTES
11
10
10
10
10
10
10
7
7
8
8
9
9
8
9
9