MT48H8M32LFB5-10:G Micron Technology Inc, MT48H8M32LFB5-10:G Datasheet - Page 27

• Manufacturer Part Number: MT48H8M32LFB5-10:G
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M32LFB5-10:G

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/8/7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 65mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

WRITE with Auto Precharge
pdf: 09005aef80d460f2, source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. D 9/04 EN
3. Interrupted by a READ (with or without auto pre-
charge): A READ to bank m will interrupt a WRITE
on bank n when registered, with the data-out
appearing CAS latency later. The precharge to
bank n will begin after
begins when the READ to bank m is registered.
The last valid WRITE to bank n will be data-in reg-
istered one clock prior to the READ to bank m
(Figure 29).
Figure 30: WRITE With Auto Precharge Interrupted by a WRITE
Figure 29: WRITE With Auto Precharge Interrupted by a READ
Internal
States
Internal
States
NOTE: 1. DQM is LOW.
NOTE: 1. DQM is LOW.
COMMAND
COMMAND
ADDRESS
t
BANK m
WR is met, where
BANK n
ADDRESS
BANK m
BANK n
CLK
DQ
CLK
DQ
Page Active
T0
NOP
Page Active
T0
NOP
WRITE - AP
WRITE - AP
BANK n,
Page Active
BANK n
BANK n,
COL a
Page Active
T1
D
BANK n
COL a
T1
D
a
IN
a
IN
WRITE with Burst of 4
WRITE with Burst of 4
t
WR
a + 1
T2
T2
a + 1
D
NOP
D
NOP
IN
IN
27
BANK m,
READ - AP
T3
COL d
a + 2
T3
BANK m
D
NOP
IN
Interrupt Burst, Write-Back
t
CAS Latency = 3 (BANK m)
WR - BANK n
READ with Burst of 4
4. Interrupted by a WRITE (with or without auto pre-
charge): A WRITE to bank m will interrupt a
WRITE on bank n when registered. The precharge
to bank n will begin after
begins when the WRITE to bank m is registered.
The last valid data WRITE to bank n will be data
registered one clock prior to a WRITE to bank m
(Figure 30).
BANK m,
WRITE - AP
T4
COL d
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T4
BANK m
NOP
D
d
t
IN
Interrupt Burst, Write-Back
WR - BANK n
WRITE with Burst of 4
T5
T5
NOP
d + 1
NOP
D
Precharge
t
RP - BANK n
IN
T6
D
NOP
T6
OUT
d
d + 2
NOP
D
t RP - BANK n
IN
Precharge
DON’T CARE
DON’T CARE
T7
D
d + 1
NOP
t RP - BANK m
OUT
T7
d + 3
NOP
D
t WR - BANK m
MOBILE SDRAM
IN
Write-Back
©2003 Micron Technology, Inc. All rights reserved.
t
WR is met, where
256Mb: x32
PRELIMINARY
t
WR