MT48H8M32LFB5-10:G Micron Technology Inc, MT48H8M32LFB5-10:G Datasheet - Page 8

• Manufacturer Part Number: MT48H8M32LFB5-10:G
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M32LFB5-10:G

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/8/7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 65mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Functional Description
banks) are quad-bank DRAMs that operate at 3.3V,
2.5V, and 1.8V and include a synchronous interface (all
signals are registered on the positive edge of the clock
signal, CLK). Each of the 67,108,864-bit banks is orga-
nized as 4,096 rows by 512 columns by 32 bits.
ented; accesses start at a selected location and con-
tinue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed
(BA0 and BA1 select the bank, A0–A11 select the row).
The address bits (A0–A8) registered coincident with
the READ or WRITE command are used to select the
starting column location for the burst access.
tialized. The following sections provide detailed infor-
mation
definition, command descriptions and device opera-
tion.
Initialization
predefined manner. Operational procedures other
than those specified may result in undefined opera-
tion. Once the power is applied to V
(simultaneously) and the clock is stable (stable clock is
defined as a signal cycling within timing constraints
specified for the clock pin), the SDRAM requires a
100µs delay prior to issuing any command other than a
COMMAND INHIBIT or NOP . Starting at some point
during this 100µs period and continuing at least
through the end of this period, Command Inhibit or
NOP commands should be applied.
one Command Inhibit or NOP command having been
applied, a PRECHARGE command should be applied.
All banks must then be precharged, thereby placing
the device in the all banks idle state.
be performed. After the AUTO refresh cycles are com-
plete, the SDRAM is ready for mode register program-
ming. Because the mode register will power up in an
unknown state, it should be loaded prior to applying
any operational command.
pdf: 09005aef80d460f2, source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. D 9/04 EN
In general, the 256Mb SDRAMs (2 Meg x 32 x4
Read and write accesses to the SDRAM are burst ori-
Prior to normal operation, the SDRAM must be ini-
SDRAMs must be powered up and initialized in a
Once the 100µs delay has been satisfied with at least
Once in the idle state, two AUTO refresh cycles must
covering
device
initialization,
DD
and V
register
DD
Q
8
Register Definition
Mode Register
are two mode registers in the Mobile component,
Mode Register and Extended Mode Register. For this
section, Mode Register is referred to. Extended Mode
register is illustrated in Figure 5. The mode register is
used to define the specific mode of operation of the
SDRAM. This definition includes the selection of a
burst length, a burst type, a CAS latency, an operating
mode and a write burst mode, as shown in Figure 3.
The mode register is programmed via the LOAD
MODE REGISTER command and will retain the stored
information until it is programmed again or the device
loses power.
M3 specifies the type of burst (sequential or inter-
leaved), M4–M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the write
burst mode, and M10, and M11 should be set to zero.
M12 and M13 should be set to zero to prevent the
extended mode register from being programmed.
are idle, and the controller must wait the specified
time before initiating the subsequent operation. Vio-
lating either of these requirements will result in
unspecified operation.
Burst Length
ented, with the burst length being programmable, as
shown in Figure 3. The burst length determines the
maximum number of column locations that can be
accessed for a given READ or WRITE command. Burst
lengths of 1, 2, 4, or 8 locations are available for both
the sequential and the interleaved burst types, and a
full-page burst is available for the sequential type. The
full-page burst is used in conjunction with the BURST
TERMINATE command to generate arbitrary burst
lengths.
operation or incompatibility with future versions may
result.
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1–A8 when the burst length is set to two;
by A2–A8 when the burst length is set to four; and by
In order to achieve low power consumption, there
Mode Register bits M0–M2 specify the burst length,
The mode register must be loaded when all banks
Read and write accesses to the SDRAM are burst ori-
Reserved states should not be used, as unknown
When a READ or WRITE command is issued, a block
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MOBILE SDRAM
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x32
PRELIMINARY