MT48H8M32LFB5-10:G Micron Technology Inc, MT48H8M32LFB5-10:G Datasheet - Page 11

• Manufacturer Part Number: MT48H8M32LFB5-10:G
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M32LFB5-10:G

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/8/7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 65mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

NOTE:
grammed with E7 through E11 set to “0”. It must be
loaded when all banks are idle and no bursts are in
progress, and the controller must wait the specified
time before initiating any subsequent operation. Vio-
lating either of these requirements results in unspeci-
fied operation. Once the values are entered the
extended mode register settings will be retained even
after exiting Deep Power Down.
Temperature Compensated Self Refresh
allows the controller to program the Refresh interval
during SELF REFRESH mode, according to the case
temperature of the Mobile device. This allows great
pdf: 09005aef80d460f2, source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. D 9/04 EN
1. E13 and E12 (BA1 and BA0) must be “1, 0” to select the
2. Default EMR values are full array for PASR, Full Drive
3. RFU: Reserved for Future Use.
4. E4 and E3 are “Don’t Care”
E6
0
0
1
1
Figure 5: Low Power Extended Mode
The low power extended mode register must be pro-
Temperature Compensated Self Refresh (TCSR)
Extended Mode Register (vs. the base Mode Register).
Strength.
E5
0
1
0
1
BA1
1
E13
13
Driver Strength
Full Strength 2
Half Strength
RFU
RFU
1
0
BA0
12
E12
All must be set to "0"
11
A11
E11
10
A10
E10
9
A9
E9
Register Table
8
A8
E8
7
A7 A6 A5 A4 A3
E7 E6 E5 E4 E3
6
DS
5
X
4
E2
0
0
0
0
1
1
1
1
X
3
E1
0
0
1
1
0
0
1
1
A2 A1 A0
E2 E1 E0
2
PASR
E0
0
1
0
1
0
1
0
1
1
Self Refresh Coverage
Four Banks 2
Two Banks (Bank 0,1)
One Bank (Bank 0)
RFU 3
RFU
1/2 Bank (Bank 0)
1/4 Bank (Bank 0)
RFU
0
Address Bus
Low Power
Extended Mode
Register (Ex)
11
power savings during SELF REFRESH during most
operating temperature ranges. Only during extreme
temperatures would the controller have to select the
maximum TCSR level. This would guarantee data dur-
ing SELF REFRESH.
the capacitor losing its charge over time. The refresh
rate is dependent on temperature. At higher tempera-
tures a capacitor loses charge quicker than at lower
temperatures, requiring the cells to be refreshed more
often. Historically, during Self Refresh, the refresh rate
has been set to accommodate the worst case, or high-
est temperature range expected.
sumed during refresh was unnecessarily high, because
the refresh rate was set to accommodate the higher
temperatures. This SDRAM has an on-chip tempera-
ture sensor that automatically adjusts refresh rate
according to die temperature. The default setting for
the TCSR is with the temperature sensor enabled.
Partial Array Self Refresh
the Partial Array Self Refresh (PASR) feature allows the
controller to select the amount of memory that will be
refreshed during SELF REFRESH. The refresh options
are all banks (banks 0, 1, 2, and 3); two banks (banks 0
and 1); and one bank (bank 0). Also included in the
refresh options are the half-bank and quarter-bank
partial array self refresh (bank 0). WRITE and READ
commands occur to any bank selected during stan-
dard operation, but only the selected banks in PASR
will be refreshed during SELF REFRESH. It’s important
to note that data in banks 2 and 3 will be lost when the
two bank option is used. Data will be lost in banks 1, 2,
and 3 when the one bank option is used.
Driver Strength
used to select the driver strength of the DQ outputs.
This value should be set according to the application’s
requirements. For H (1.8V) and V (2.5V) versions, full
drive strength has a target impedance of 25-30
half drive strength has a target of 55-60 . The LC ver-
sion (3.3V) is targeting 18-20
half drive.
Every cell in the DRAM requires refreshing due to
Thus, during ambient temperatures, the power con-
For further power savings during SELF REFRESH,
Bits E5 and E6 of the extended mode register can be
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MOBILE SDRAM
©2003 Micron Technology, Inc. All rights reserved.
full drive and 35-40
256Mb: x32
PRELIMINARY
and