MT48H8M32LFB5-10:G Micron Technology Inc, MT48H8M32LFB5-10:G Datasheet - Page 21

• Manufacturer Part Number: MT48H8M32LFB5-10:G
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M32LFB5-10:G

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/8/7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 65mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

BURST TERMINATE command, and fixed-length
READ bursts may be truncated with a BURST TERMI-
NATE command, provided that auto precharge was
not activated. The BURST TERMINATE command
pdf: 09005aef80d460f2, source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. D 9/04 EN
Full-page READ bursts can be truncated with the
COMMAND
COMMAND
COMMAND
ADDRESS
ADDRESS
ADDRESS
NOTE: DQM is LOW.
CLK
CLK
CLK
DQ
DQ
DQ
Figure 15: Terminating a READ Burst
CAS Latency = 1
BANK,
BANK,
T0
COL n
T0
COL n
T0
BANK,
COL n
READ
READ
READ
CAS Latency = 2
CAS Latency = 3
T1
T1
T1
NOP
NOP
NOP
D
OUT
n
T2
T2
T2
NOP
NOP
NOP
D
D
n + 1
OUT
OUT
n
T3
T3
T3
NOP
NOP
21
NOP
D
n + 2
D
n + 1
D
OUT
OUT
OUT
n
should be issued x cycles before the clock edge at
which the last desired data element is valid, where x
equals the CAS latency minus one. This is shown in
Figure 15 for each possible CAS latency; data element
n + 3 is the last desired data element of a longer burst.
TERMINATE
TERMINATE
TERMINATE
T4
BURST
T4
BURST
BURST
T4
X = 0 cycles
X = 1 cycle
D
D
n + 3
n + 2
D
n + 1
OUT
OUT
OUT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X = 2 cycles
T5
T5
T5
NOP
NOP
NOP
D
n + 3
D
n + 2
OUT
OUT
T6
T6
T6
NOP
NOP
NOP
D
n + 3
OUT
DON’T CARE
T7
NOP
MOBILE SDRAM
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x32
PRELIMINARY