MT48H8M32LFB5-10:G Micron Technology Inc, MT48H8M32LFB5-10:G Datasheet - Page 15

• Manufacturer Part Number: MT48H8M32LFB5-10:G
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M32LFB5-10:G

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/8/7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 65mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Operation
Bank/Row Activation
issued to a bank within the SDRAM, a row in that bank
must be “opened.” This is accomplished via the
ACTIVE command, which selects both the bank and
the row to be activated (see Figure 6).
a READ or WRITE command may be issued to that row,
subject to the
be divided by the clock period and rounded up to the
next whole number to determine the earliest clock
edge after the ACTIVE command on which a READ or
WRITE command can be entered. For example, a
specification of 20ns with a 125 MHz clock (8ns
period) results in 2.5 clocks, rounded to 3. This is
reflected in Figure 7, which covers any case where 2 <
t
convert other specification limits from time units to
clock cycles.)
in the same bank can only be issued after the previous
active row has been “closed” (precharged). The mini-
mum time interval between successive ACTIVE com-
mands to the same bank is defined by
can be issued while the first bank is being accessed,
which results in a reduction of total row-access over-
head. The minimum time interval between successive
ACTIVE commands to different banks is defined by
t
pdf: 09005aef80d460f2, source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. D 9/04 EN
RCD (MIN)/
RRD.
Before any READ or WRITE commands can be
After opening a row (issuing an ACTIVE command),
A subsequent ACTIVE command to a different row
A subsequent ACTIVE command to another bank
Figure 7: Example: Meeting
t
CK
t
RCD specification.
3. (The same procedure is used to
COMMAND
CLK
ACTIVE
T0
t
RCD (MIN) should
t
RC.
NOP
T1
t
RCD
t
RCD (MIN) When 2 <
t
RCD
15
Figure 6: Activating a Specific Row in a
T2
A0–A10, A11
NOP
BA0, BA1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RAS#
CAS#
WE#
CKE
CLK
CS#
READ or
WRITE
T3
HIGH
Specific Bank
DON’T CARE
t
RCD (MIN)/
MOBILE SDRAM
T4
©2003 Micron Technology, Inc. All rights reserved.
ADDRESS
ADDRESS
BANK
ROW
256Mb: x32
t
PRELIMINARY
CK< 3
DON’T CARE