MT48H8M32LFB5-10:G Micron Technology Inc, MT48H8M32LFB5-10:G Datasheet - Page 32

• Manufacturer Part Number: MT48H8M32LFB5-10:G
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M32LFB5-10:G

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/8/7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 65mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank will
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m inter-
pdf: 09005aef80d460f2, source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. D 9/04 EN
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge
8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has been interrupted
9. Burst in bank n continues as initiated.
enabled and READs or WRITEs with auto precharge disabled.
by bank m’s burst.
interrupt the READ on bank n, CAS latency later (Figure 10 consecutive read bursts).
interrupt the READ on bank n when registered (Figures 12 and 13). DQM should be used one clock prior to the WRITE
command to prevent bus contention.
interrupt the WRITE on bank n when registered (Figure 20), with the data-out appearing CAS latency later. The last valid
WRITE to bank n will be data-in registered one clock prior to the READ to bank m.
interrupt the WRITE on bank n when registered (Figure 18). The last valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m.
interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is reg-
istered.
interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent
bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered.
interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to
bank n will begin after
n will be data-in registered one clock prior to the READ to bank m.
rupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after
when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock to the WRITE
to bank m.
t
WR is met, where
t
WR begins when the READ to bank m is registered. The last valid WRITE bank
32
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
WR is met, where
MOBILE SDRAM
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x32
PRELIMINARY
t
WR begins