HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 95

• Manufacturer Part Number: HD64F36077GHV
• Description: 16BIT MCU FLASH 56K, SMD, LQFP64
• Manufacturer: Renesas Electronics America

Specifications of HD64F36077GHV

• No. Of I/o's: 47
• Ram Memory Size: 4KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 4.5V
• Core Size: 16bit
• Program Memory Size: 56KB
• Oscillator Type: External Only
• Controller Family/series: H8/300H
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.2
When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an
interrupt request to the CPU. The ABIF bit in ABRKSR is set to 1 by the combination of the
address set in BAR, the data set in BDR, and the conditions set in ABRKCR. When the interrupt
request is accepted, interrupt exception handling starts after the instruction being executed ends.
The address break interrupt is not masked by the I bit in CCR of the CPU.
Figures 4.2 show the operation examples of the address break interrupt setting.
When the address break is specified in instruction execution cycle
Operation
Register setting
• ABRKCR = H'80
• BAR = H'025A
φ
Address
bus
Interrupt
request
Figure 4.2 Address Break Interrupt Operation Example (1)
prefetch
instruc-
NOP
0258
tion
prefetch
instruc-
NOP
Program
*
025A
tion
0258
025A
025C
0260
0262
:
Interrupt acceptance
prefetch
instruc-
tion 1
MOV
NOP
NOP
MOV.W @H'025A,R0
NOP
NOP
025C
:
prefetch
instruc-
tion 2
MOV
025E
processing
Internal
Underline indicates the address
to be stacked.
Rev. 1.00 Sep. 16, 2005 Page 65 of 490
SP-2
Stack save
SP-4
Section 4 Address Break
REJ09B0216-0100