HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 316

16BIT MCU FLASH 56K, SMD, LQFP64

HD64F36077GHV

Manufacturer Part Number
HD64F36077GHV
Description
16BIT MCU FLASH 56K, SMD, LQFP64
Manufacturer
Renesas Electronics America
Datasheet

Specifications of HD64F36077GHV

No. Of I/o's
47
Ram Memory Size
4KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Supply Voltage Range
4.5V
Core Size
16bit
Program Memory Size
56KB
Oscillator Type
External Only
Controller Family/series
H8/300H
Peripherals
ADC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Manufacturer
Quantity
Price
Part Number:
HD64F36077GHV
Manufacturer:
RENESAS
Quantity:
340
Part Number:
HD64F36077GHV
Manufacturer:
Renesas
Quantity:
200
Part Number:
HD64F36077GHV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 16 Serial Communication Interface 3 (SCI3)
16.3.7
SSR is a register containing status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared.
Rev. 1.00 Sep. 16, 2005 Page 286 of 490
REJ09B0216-0100
Bit
7
6
5
4
Bit Name
TDRE
RDRF
OER
FER
Serial Status Register (SSR)
Initial
Value
1
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
[Clearing conditions]
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
[Clearing conditions]
Overrun Error
[Setting condition]
[Clearing condition]
Framing Error
[Setting condition]
[Clearing condition]
When the TE bit in SCR3 is 0
When data is transferred from TDR to TSR
When 0 is written to TDRE after reading TDRE = 1
When the transmit data is written to TDR
When serial reception ends normally and receive data
is transferred from RSR to RDR
When 0 is written to RDRF after reading RDRF = 1
When data is read from RDR
When an overrun error occurs in reception
When 0 is written to OER after reading OER = 1
When a framing error occurs in reception
When 0 is written to FER after reading FER = 1

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