HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 365

• Manufacturer Part Number: HD64F36077GHV
• Description: 16BIT MCU FLASH 56K, SMD, LQFP64
• Manufacturer: Renesas Electronics America

Specifications of HD64F36077GHV

• No. Of I/o's: 47
• Ram Memory Size: 4KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 4.5V
• Core Size: 16bit
• Program Memory Size: 56KB
• Oscillator Type: External Only
• Controller Family/series: H8/300H
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.3.6
SAR selects the communication format and sets the slave address. When the chip is in slave mode
with the I
received after a start condition, the chip operates as the slave device.
Bit
1
0
Bit
7 to 1
0
Bit Name
AAS
ADZ
Bit Name
SVA6 to
SVA0
FS
2
Slave Address Register (SAR)
C bus format, if the upper 7 bits of SAR match the upper 7 bits of the first frame
Initial
Value
0
0
Initial
Value
All 0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Slave Address Recognition Flag
In slave receive mode, this flag is set to 1 if the first frame
following a start condition matches bits SVA6 to SVA0 in
SAR.
[Setting conditions]
•
•
[Clearing condition]
•
General Call Address Recognition Flag
This bit is valid in I
[Setting condition]
•
[Clearing condition]
•
Description
Slave Address 6 to 0
These bits set a unique address in bits SVA6 to SVA0,
differing form the addresses of other slave devices
connected to the I
Format Select
0: I
1: Clock synchronous serial format is selected.
2
When the slave address is detected in slave receive
mode
When the general call address is detected in slave
receive mode.
When 0 is written in AAS after reading AAS=1
When the general call address is detected in slave
receive mode
When 0 is written in ADZ after reading ADZ=1
C bus format is selected.
2
2
C bus.
C bus format slave receive mode.
Rev. 1.00 Sep. 16, 2005 Page 335 of 490
Section 17 I
2
C Bus Interface 2 (IIC2)
REJ09B0216-0100