HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 390

• Manufacturer Part Number: HD64F36077GHV
• Description: 16BIT MCU FLASH 56K, SMD, LQFP64
• Manufacturer: Renesas Electronics America

Specifications of HD64F36077GHV

• No. Of I/o's: 47
• Ram Memory Size: 4KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 4.5V
• Core Size: 16bit
• Program Memory Size: 56KB
• Oscillator Type: External Only
• Controller Family/series: H8/300H
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 18 A/D Converter
18.3
The A/D converter has the following registers.
• A/D data register A (ADDRA)
• A/D data register B (ADDRB)
• A/D data register C (ADDRC)
• A/D data register D (ADDRD)
• A/D control/status register (ADCSR)
• A/D control register (ADCR)
18.3.1
There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of
A/D conversion. The ADDR registers, which store a conversion result for each analog input
channel, are shown in table 18.2.
The converted 10-bit data is stored in bits 15 to 6. The lower 6 bits are always read as 0.
The data bus width between the CPU and the A/D converter is 8 bits. The upper byte can be read
directly from the CPU, however the lower byte should be read via a temporary register. The
temporary register contents are transferred from the ADDR when the upper byte data is read.
When reading ADDR, read the upper byte first then the lower one, or read in word units. The
ADDR is initialized to H'0000.
Table 18.2 Analog Input Channels and Corresponding ADDR Registers
Rev. 1.00 Sep. 16, 2005 Page 360 of 490
REJ09B0216-0100
Group 0
AN0
AN1
AN2
AN3
Analog Input Channel
Register Descriptions
A/D Data Registers A to D (ADDRA to ADDRD)
Group 1
AN4
AN5
AN6
AN7
A/D Data Register to Be Stored Results of A/D Conversion
ADDRA
ADDRB
ADDRC
ADDRD