HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 312

• Manufacturer Part Number: HD64F36077GHV
• Description: 16BIT MCU FLASH 56K, SMD, LQFP64
• Manufacturer: Renesas Electronics America

Specifications of HD64F36077GHV

• No. Of I/o's: 47
• Ram Memory Size: 4KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 4.5V
• Core Size: 16bit
• Program Memory Size: 56KB
• Oscillator Type: External Only
• Controller Family/series: H8/300H
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 16 Serial Communication Interface 3 (SCI3)
16.3.4
TDR is an 8-bit register that stores data for transmission. When the SCI3 detects that TSR is
empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-
buffered structure of TDR and TSR enables continuous serial transmission. If the next transmit
data has already been written to TDR during transmission of one-frame data, the SCI3 transfers
the written data to TSR to continue transmission. To achieve reliable serial transmission, write
transmit data to TDR only once after confirming that the TDRE bit in SSR is set to 1. TDR is
initialized to H'FF.
16.3.5
SMR is used to set the SCI3’s serial transfer format and select the baud rate generator clock
source.
Rev. 1.00 Sep. 16, 2005 Page 282 of 490
REJ09B0216-0100
Bit
7
6
5
4
Bit Name
COM
CHR
PE
PM
Transmit Data Register (TDR)
Serial Mode Register (SMR)
Initial
Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Communication Mode
0: Asynchronous mode
1: Clock synchronous mode
Character Length (enabled only in asynchronous mode)
0: Selects 8 bits as the data length.
1: Selects 7 bits as the data length.
Parity Enable (enabled only in asynchronous mode)
When this bit is set to 1, the parity bit is added to transmit
data before transmission, and the parity bit is checked in
reception.
Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.