HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet
HD64F36077GHV
Specifications of HD64F36077GHV
Available stocks
Related parts for HD64F36077GHV
HD64F36077GHV Summary of contents
Page 1
REJ09B0216-0100 16 Rev.1.00 Revision Date: Sep. 16, 2005 H8/36077 Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series H8/36077GF H8/36074GF Group Hardware Manual HD64F36077G HD64F36074G ...
Page 2
Rev. 1.00 Sep. 16, 2005 Page ii of xxx ...
Page 3
Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
Page 4
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
Page 5
Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip ...
Page 6
The H8/36077 Group are single-chip microcomputers made up of the high-speed H8/300H CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set that is compatible ...
Page 7
Notes: When using an on-chip emulator (E7, E8) for H8/36077 program development and debugging, the following restrictions must be noted. 1. The NMI pin is reserved for the E7 or E8, and cannot be used. 2. Pins P85, P86, and ...
Page 8
H8/36077 Group manuals: Document Title H8/36077 Group Hardware Manual H8/300H Series Programming Manual User's manuals for development tools: Document Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual Microcomputer Development Environment System H8S, H8/300 Series Simulator/Debugger User's ...
Page 9
Section 1 Overview................................................................................................1 1.1 Features.................................................................................................................................. 1 1.2 Block Diagram ....................................................................................................................... 3 1.3 Pin Arrangement .................................................................................................................... 4 1.4 Pin Functions ......................................................................................................................... 5 Section 2 CPU........................................................................................................9 2.1 Address Space and Memory Map ........................................................................................ 10 2.2 Register Configuration......................................................................................................... 11 2.2.1 General Registers.................................................................................................... 12 ...
Page 10
Interrupt Enable Register 2 (IENR2) ...................................................................... 49 3.2.5 Interrupt Flag Register 1 (IRR1)............................................................................. 49 3.2.6 Interrupt Flag Register 2 (IRR2)............................................................................. 51 3.2.7 Wakeup Interrupt Flag Register (IWPR) ................................................................ 51 3.3 Reset Exception Handling.................................................................................................... 53 3.4 Interrupt Exception Handling .............................................................................................. ...
Page 11
Pin Connection when Not Using Subclock............................................................. 86 5.7 Prescaler............................................................................................................................... 87 5.7.1 Prescaler S .............................................................................................................. 87 5.7.2 Prescaler W............................................................................................................. 87 5.8 Usage Notes ......................................................................................................................... 88 5.8.1 Note on Resonators................................................................................................. 88 5.8.2 Notes on Board Design ........................................................................................... 88 Section 6 Power-Down ...
Page 12
Program/Erase Protection .................................................................................................. 118 7.5.1 Hardware Protection ............................................................................................. 118 7.5.2 Software Protection .............................................................................................. 118 7.5.3 Error Protection .................................................................................................... 118 7.6 Programmer Mode ............................................................................................................. 119 7.7 Power-Down States for Flash Memory.............................................................................. 119 Section 8 RAM .................................................................................................. 121 Section 9 I/O ...
Page 13
Port Control Register 8 (PCR8) ............................................................................ 151 9.7.2 Port Data Register 8 (PDR8)................................................................................. 151 9.7.3 Pin Functions ........................................................................................................ 152 9.8 Port B ................................................................................................................................. 153 9.8.1 Port Data Register B (PDRB) ............................................................................... 153 9.8.2 Pin Functions ........................................................................................................ 154 9.9 Port ...
Page 14
Section 12 Timer V ........................................................................................... 177 12.1 Features.............................................................................................................................. 177 12.2 Input/Output Pins............................................................................................................... 179 12.3 Register Descriptions......................................................................................................... 179 12.3.1 Timer Counter V (TCNTV).................................................................................. 179 12.3.2 Time Constant Registers A and B (TCORA, TCORB) ........................................ 180 12.3.3 Timer Control Register V0 (TCRV0) ...
Page 15
Reset Synchronous PWM Mode ........................................................................... 232 13.4.7 Complementary PWM Mode................................................................................ 236 13.4.8 Buffer Operation ................................................................................................... 246 13.4.9 Timer Z Output Timing ........................................................................................ 254 13.5 Interrupts............................................................................................................................ 257 13.5.1 Status Flag Set Timing.......................................................................................... 257 13.5.2 Status Flag Clearing Timing ................................................................................. 259 ...
Page 16
Data Transmission ................................................................................................ 297 16.4.4 Serial Data Reception ........................................................................................... 299 16.5 Operation in Clock Synchronous Mode............................................................................. 303 16.5.1 Clock..................................................................................................................... 303 16.5.2 SCI3 Initialization................................................................................................. 303 16.5.3 Serial Data Transmission ...................................................................................... 304 16.5.4 Serial Data Reception (Clock Synchronous Mode) .............................................. 306 ...
Page 17
Noise Filter ........................................................................................................... 349 17.4.8 Example of Use..................................................................................................... 349 17.5 Interrupt Request................................................................................................................ 354 17.6 Bit Synchronous Circuit..................................................................................................... 355 17.7 Usage Notes ....................................................................................................................... 356 17.7.1 Issue (Retransmission) of Start/Stop Conditions .................................................. 356 17.7.2 WAIT Setting in I Section 18 A/D ...
Page 18
Section 21 List of Registers............................................................................... 385 21.1 Register Addresses (Address Order).................................................................................. 386 21.2 Register Bits....................................................................................................................... 393 21.3 Registers States in Each Operating Mode.......................................................................... 399 Section 22 Electrical Characteristics ................................................................. 405 22.1 Absolute Maximum Ratings .............................................................................................. 405 22.2 Electrical Characteristics (F-ZTAT™ ...
Page 19
Section 1 Overview Figure 1.1 Block Diagram of H8/36077 Group .............................................................................. 3 Figure 1.2 Pin Arrangements of H8/36077 Group (FP-64K, FP-64A)........................................... 4 Section 2 CPU Figure 2.1 Memory Map............................................................................................................... 10 Figure 2.2 CPU Registers ............................................................................................................. 11 Figure 2.3 Usage of ...
Page 20
Figure 5.5 Flowchart of Clock Switching with Backup Function Disabled (2) (From External Clock to On-Chip Oscillator Clock)................................................... 78 Figure 5.6 Timing Chart of Switching from On-Chip Oscillator Clock to External Clock .......... 79 Figure 5.7 Timing Chart to Switch ...
Page 21
Section 11 Timer B1 Figure 11.1 Block Diagram of Timer B1.................................................................................... 171 Section 12 Timer V Figure 12.1 Block Diagram of Timer V...................................................................................... 178 Figure 12.2 Increment Timing with Internal Clock .................................................................... 185 Figure 12.3 Increment Timing with External Clock ...
Page 22
Figure 13.22 Example of PWM Mode Operation (1) ................................................................. 228 Figure 13.23 Example of PWM Mode Operation (2) ................................................................. 229 Figure 13.24 Example of PWM Mode Operation (3) ................................................................. 230 Figure 13.25 Example of PWM Mode Operation (4) ................................................................. 231 ...
Page 23
Figure 13.55 Contention between TCNT Write and Overflow................................................... 262 Figure 13.56 Contention between GR Read and Input Capture.................................................. 263 Figure 13.57 Contention between Count Clearing and Increment Operations by Input Capture.................................................................................................... 264 Figure 13.58 Contention between GR Write and Input ...
Page 24
Figure 16.18 Example of SCI3 Reception Using Multiprocessor Format (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).............................. 316 Figure 16.19 Receive Data Sampling Timing in Asynchronous Mode ...................................... 319 2 Section Bus Interface 2 (IIC2) Figure ...
Page 25
Figure 19.6 Operational Timing of LVDI Circuit (When Compared Voltage is Input through ExtU and ExtD Pins).......................... 381 Figure 19.7 Timing of Setting Bits in Reset Source Decision Register...................................... 382 Section 20 Power Supply Circuit Figure 20.1 Power Supply Connection ...
Page 26
Figure B.26 Port B Block Diagram (PC0).................................................................................. 482 Figure D.1 FP-64K Package Dimensions ................................................................................... 485 Figure D.2 FP-64A Package Dimensions ................................................................................... 486 Rev. 1.00 Sep. 16, 2005 Page xxvi of xxx ...
Page 27
Section 1 Overview Table 1.1 Pin Functions ............................................................................................................ 5 Section 2 CPU Table 2.1 Operation Notation ................................................................................................. 18 Table 2.2 Data Transfer Instructions....................................................................................... 19 Table 2.3 Arithmetic Operations Instructions (1) ................................................................... 20 Table 2.3 Arithmetic Operations Instructions (2) ................................................................... 21 ...
Page 28
Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible ............................................................................................................. 112 Table 7.4 Reprogram Data Computation Table .................................................................... 115 Table 7.5 Additional-Program Data Computation Table ...................................................... 115 Table 7.6 Programming Time ............................................................................................... 115 Table ...
Page 29
Table 16.6 SSR Status Flags and Receive Data Handling ...................................................... 300 Table 16.7 SCI3 Interrupt Requests........................................................................................ 317 2 Section Bus Interface 2 (IIC2) 2 Table 17 Bus Interface Pins........................................................................................... 323 Table 17.2 Transfer Rate ........................................................................................................ ...
Page 30
Rev. 1.00 Sep. 16, 2005 Page xxx of xxx ...
Page 31
Features • High-speed H8/300H CPU with an internal 16-bit architecture Upward-compatible with H8/300 CPU at the object level Sixteen 16-bit general registers 62 basic instructions • Various peripheral functions RTC (can be used as a ...
Page 32
Section 1 Overview • On-chip memory Product Classification Flash memory version H8/36077F HD64F36077G TM (F-ZTAT version) H8/36074F HD64F36074G • General I/O ports I/O pins: 47 I/O pins, including 8 large current ports (I Input-only pins: 8 input pins ...
Page 33
Block Diagram External Subclock clock oscillator oscillator P10/TMOW P11/PWM P12 P14/IRQ0 P15/IRQ1/TMIB1 P16/IRQ2 P17/IRQ3/TRGV P20/SCK3 P21/RXD P22/TXD P23 P24 P30 P31 P32 P33 P34 P35 P36 P37 P57/SCL P56/SDA P55/WKP5/ADTRG P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0 Figure 1.1 Block Diagram ...
Page 34
Section 1 Overview 1.3 Pin Arrangement P71/RXD_2 50 P72/TXD_2 P14/IRQ0 51 52 P15/IRQ1/TMIB1 53 P16/IRQ2 54 P17/IRQ3/TRGV 55 P33 56 P32 57 P31 ...
Page 35
Pin Functions Table 1.1 Pin Functions Pin No. FP-64K Type Symbol FP-64A Power source pins Clock pins OSC1 11 OSC2/ 10 CLKOUT RES ...
Page 36
Section 1 Overview Pin No. FP-64K Type Symbol FP-64A Timer V TMOV 30 TMCIV 29 TMRIV 28 TRGV 54 Timer Z FTIOA0 36 FTIOB0 34 FTIOC0 33 FTIOD0 32 FTIOA1 37 FTIOB1 FTIOD1 14-bit PWM PWM ...
Page 37
Pin No. FP-64K Type Symbol FP-64A A/D AN7 to AN0 2, 1 converter 64 ADTRG 22 I/O ports PB7 to PB0 PC1, PC0 10, 11 P17 to P14, 54 ...
Page 38
Section 1 Overview Rev. 1.00 Sep. 16, 2005 Page 8 of 490 REJ09B0216-0100 ...
Page 39
This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with the H8/300CPU, and supports only normal mode, which has a 64-kbyte address space. • Upward-compatible with H8/300 CPUs Can execute H8/300 CPUs object programs ...
Page 40
Section 2 CPU • Power-down state Transition to power-down state by SLEEP instruction 2.1 Address Space and Memory Map The address space of this LSI is 64 kbytes, which includes the program area and the data area. Figures 2.1 ...
Page 41
Register Configuration The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition-code register (CCR). ...
Page 42
Section 2 CPU 2.2.1 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a ...
Page 43
SP (ER7) Figure 2.4 Relationship between Stack Pointer and Stack Area 2.2.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), ...
Page 44
Section 2 CPU Initial Bit Bit Name Value Undefined R Undefined R Undefined R Undefined R Undefined R Undefined R Undefined R/W Rev. ...
Page 45
Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte operand data. ...
Page 46
Section 2 CPU Data Type General Data Format Register Word data Rn Word data En 15 MSB Longword ERn data 31 MSB [Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: ...
Page 47
Memory Data Formats Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address attempt is made ...
Page 48
Section 2 CPU 2.4 Instruction Set 2.4.1 Table of Instructions Classified by Function The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined ...
Page 49
Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers ( E7), and 32-bit registers/address register (ER0 to ER7). Table 2.2 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs ...
Page 50
Section 2 CPU Table 2.3 Arithmetic Operations Instructions (1) Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD B/W/L SUB Performs addition or subtraction on data in two general registers immediate data and ...
Page 51
Table 2.3 Arithmetic Operations Instructions (2) Instruction Size* Function Rd ÷ Rs → Rd DIVXS B/W Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ...
Page 52
Section 2 CPU Table 2.4 Logic Operations Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd AND B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ...
Page 53
Table 2.6 Bit Manipulation Instructions (1) Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET B Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the ...
Page 54
Section 2 CPU Table 2.6 Bit Manipulation Instructions (2) Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR B XORs the carry flag with a specified bit in a general register or memory operand and stores the result ...
Page 55
Table 2.7 Branch Instructions Instruction Size Function Bcc* Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE ...
Page 56
Section 2 CPU Table 2.8 System Control Instructions Instruction Size* Function TRAPA Starts trap-instruction exception handling. RTE Returns from an exception-handling routine. SLEEP Causes a transition to a power-down state. (EAs) → CCR LDC B/W Moves the ...
Page 57
Table 2.9 Block Data Transfer Instructions Instruction Size Function if R4L ≠ 0 then EEPMOV.B else next; ≠ 0 then EEPMOV.W else next; Transfers a data block. Starting from the address set in ER5, transfers data ...
Page 58
Section 2 CPU 2.4.2 Basic Instruction Formats H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.7 shows ...
Page 59
Addressing Modes and Effective Address Calculation The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits. 2.5.1 Addressing Modes The H8/300H CPU ...
Page 60
Section 2 CPU Register Indirect@ERn The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of the operand on memory. Register Indirect with Displacement@(d:16, ERn) or @(d:24, ERn) A ...
Page 61
Table 2.11 Absolute Address Access Ranges Absolute Address 8 bits (@aa:8) 16 bits (@aa:16) 24 bits (@aa:24) Immediate#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, ...
Page 62
Section 2 CPU Figure 2.8 Branch Address Specification in Memory Indirect Mode 2.5.2 Effective Address Calculation Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI the upper 8 bits of the effective address are ...
Page 63
Table 2.12 Effective Address Calculation (2) Addressing Mode and Instruction Format Absolute address Immediate [Legend] r, rm,rn : Register field op : Operation field disp : Displacement IMM : Immediate data abs : Absolute address Effective Address Calculation PC contents ...
Page 64
Section 2 CPU 2.6 Basic Bus Cycle CPU operation is synchronized by a system clock (φ subclock (φ edge of φ or φ to the next rising edge is called one state. A bus cycle consists of two ...
Page 65
On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and number of accessing ...
Page 66
Section 2 CPU 2.7 CPU States There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active mode and subactive mode. For the program halt state, there are ...
Page 67
Reset state Reset occurs Program halt state 2.8 Usage Notes 2.8.1 Notes on Data Access to Empty Areas The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to ...
Page 68
Section 2 CPU (1) Bit Manipulation for Two Registers Assigned to the Same Address Example 1: Bit manipulation for the timer load register and timer counter (Applicable for timer B1 in the H8/36077 Group.) Figure 2.13 shows an example of ...
Page 69
Prior to executing BSET instruction P57 P56 Input/output Input Input Pin state Low High level level PCR5 0 0 PDR5 1 0 • BSET instruction executed instruction BSET #0, @PDR5 • After executing BSET instruction P57 P56 Input/output Input ...
Page 70
Section 2 CPU • Prior to executing BSET instruction MOV.B #80, R0L MOV.B R0L, @RAM0 MOV.B R0L, @PDR5 P57 P56 Input/output Input Input Pin state Low High level level PCR5 0 0 PDR5 1 0 RAM0 1 0 • BSET ...
Page 71
Bit manipulation in a register containing a write-only bit Example 3: BCLR instruction executed designating port 5 control register PCR5 P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at ...
Page 72
Section 2 CPU • Prior to executing BCLR instruction MOV.B #3F, R0L MOV.B R0L, @RAM0 MOV.B R0L, @PCR5 P57 P56 Input/output Input Input Pin state Low High level level PCR5 0 0 PDR5 1 0 RAM0 0 0 • BCLR ...
Page 73
Section 3 Exception Handling Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts. • Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES ...
Page 74
Section 3 Exception Handling 3.1 Exception Sources and Vector Address Table 3.1 shows the vector addresses and priority of each exception handling. When more than one interrupt is requested, handling is performed from the interrupt with the highest priority. Table ...
Page 75
Relative Module Exception Sources IIC2 Transmit data empty Transmit end Receive data full Arbitration lost/Overrun error NACK detection Stop conditions detected A/D converter A/D conversion end Timer Z Compare match/input capture Timer Z overflow Compare match/input capture ...
Page 76
Section 3 Exception Handling 3.2 Register Descriptions Interrupts are controlled by the following registers. • Interrupt edge select register 1 (IEGR1) • Interrupt edge select register 2 (IEGR2) • Interrupt enable register 1 (IENR1) • Interrupt enable register 2 (IENR2) ...
Page 77
Interrupt Edge Select Register 2 (IEGR2) IEGR2 selects the direction of an edge that generates interrupt requests of the pins ADTRG and WKP5 to WKP0. Initial Bit Bit Name Value All 1 5 WPEG5 0 4 ...
Page 78
Section 3 Exception Handling 3.2.3 Interrupt Enable Register 1 (IENR1) IENR1 enables direct transition interrupts, RTC interrupts, and external pin interrupts. Initial Bit Bit Name Value 7 IENDT 0 6 IENTA 0 5 IENWP 0 IEN3 ...
Page 79
Interrupt Enable Register 2 (IENR2) IENR2 enables, timer B1 overflow interrupts. Initial Bit Bit Name Value All 0 5 IENTB1 0 All 1 When disabling interrupts by clearing bits in an interrupt ...
Page 80
Section 3 Exception Handling Initial Bit Bit Name Value 6 IRRTA 0 All 1 3 IRRI3 0 2 IRRI2 0 1 IRRI1 0 0 IRRl0 0 Rev. 1.00 Sep. 16, 2005 Page 50 of 490 REJ09B0216-0100 R/W ...
Page 81
Interrupt Flag Register 2 (IRR2) IRR2 is a status flag register for timer B1 overflow interrupts. Initial Bit Bit Name Value All 0 5 IRRTB1 0 All 1 3.2.7 Wakeup Interrupt Flag ...
Page 82
Section 3 Exception Handling Initial Bit Bit Name Value 3 IWPF3 0 2 IWPF2 0 1 IWPF1 0 0 IWPF0 0 Rev. 1.00 Sep. 16, 2005 Page 52 of 490 REJ09B0216-0100 R/W Description R/W WKP3 Interrupt Request Flag [Setting condition] ...
Page 83
Reset Exception Handling When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure ...
Page 84
Section 3 Exception Handling 3.4 Interrupt Exception Handling 3.4.1 External Interrupts As the external interrupts, there are NMI, IRQ3 to IRQ0, and WKP5 to WKP0 interrupts. (1) NMI Interrupt NMI interrupt is requested by input signal edge to pin NMI. ...
Page 85
RES ø Internal address bus Internal read signal Internal write signal Internal data bus (16 bits) (1) Reset exception handling vector address (H'0000) (2) Program start address (3) Initial program instruction Figure 3.1 Reset Sequence Section 3 Exception Handling Reset ...
Page 86
Section 3 Exception Handling 3.4.2 Internal Interrupts Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to enable or disable the interrupt. For RTC interrupt requests and direct transfer interrupt requests generated ...
Page 87
SP – – – – (R7) Stack area Prior to start of interrupt exception handling [Legend Upper 8 bits of program counter (PC Lower 8 bits ...
Page 88
Section 3 Exception Handling Rev. 1.00 Sep. 16, 2005 Page 58 of 490 REJ09B0216-0100 Figure 3.3 Interrupt Sequence ...
Page 89
Usage Notes 3.5.1 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, ...
Page 90
Section 3 Exception Handling Rev. 1.00 Sep. 16, 2005 Page 60 of 490 REJ09B0216-0100 ...
Page 91
Section 4 Address Break The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR. Break conditions that can ...
Page 92
Section 4 Address Break 4.1 Register Descriptions Address break has the following registers. • Address break control register (ABRKCR) • Address break status register (ABRKSR) • Break address register (BARH, BARL) • Break data register (BDRH, BDRL) 4.1.1 Address Break ...
Page 93
Initial Bit Bit Name Value 1 DCMP1 0 0 DCMP0 0 [Legend] X: Don't care. When an address break is set in the data read cycle or data write cycle, the data bus used will depend on the combination of ...
Page 94
Section 4 Address Break 4.1.2 Address Break Status Register (ABRKSR) ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit. Initial Bit Bit Name Value 7 ABIF 0 6 ABIE 0 ...
Page 95
Operation When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an interrupt request to the CPU. The ABIF bit in ABRKSR is set the combination of the address ...
Page 96
Section 4 Address Break When the address break is specified in the data read cycle Register setting • ABRKCR = H'A0 • BAR = H'025A MOV instruc- tion 1 prefetch φ Address 025C bus Interrupt request Figure 4.2 Address Break ...
Page 97
Section 5 Clock Pulse Generator The clock pulse generator (CPG) consists of a system clock generating circuitry, a subclock generating circuitry, and two prescalers. The system clock generating circuitry includes an external clock oscillator, a duty correction circuit, an on-chip ...
Page 98
Section 5 Clock Pulse Generator 5.1 Features Choice of two clock sources On-chip oscillator clock Clock by an external oscillator output Choice of two types of RC oscillation frequency by the user software 16 MHz 20 MHz Frequency trimming Since ...
Page 99
RC Control Register (RCCR) RCCR controls the on-chip oscillator. Initial Bit Bit Name Value 7 RCSTP 0 6 FSEL 1 5 VCLSEL All 0 1 RCPSC1 1 0 RCPSC0 0 R/W Description R/W On-Chip Oscillator ...
Page 100
Section 5 Clock Pulse Generator 5.2.2 RC Trimming Data Protect Register (RCTRMDPR) RCTRMDPR controls RCTRMDPR itself and writing to RCTRMDR. Use the MOV instruction to rewrite this register. Bit manipulation instruction cannot change the settings. Initial Bit Bit Name Value ...
Page 101
Initial Bit Bit Name Value 4 0 TRMDRWE All 1 5.2.3 RC Trimming Data Register (RCTRMDR) RCTRMDR stores the trimming data of the on-chip oscillator frequency (FSEL = 1, 20 MHz). Initial Bit Bit Name Value 7 ...
Page 102
Section 5 Clock Pulse Generator 5.2.4 Clock Control/Status Register (CKCSR) CKCSR selects the port C function, controls switching the system clocks, and indicates the system clock state. Initial Bit Bit Name Value 7 PMRC1 0 6 PMRC0 0 5 OSCBAKE ...
Page 103
Initial Bit Bit Name Value 4 OSCSEL 0 3 CKSWIE 0 2 CKSWIF 0 R/W Description R/W LSI Operating Clock Select When OSCBAKE This bit is used to forcibly select the system clock of this LSI. 0: The on-chip oscillator ...
Page 104
Section 5 Clock Pulse Generator Initial Bit Bit Name Value 1 OSCHLT 1 0 CKSTA 0 Rev. 1.00 Sep. 16, 2005 Page 74 of 490 REJ09B0216-0100 R/W Description R External Oscillator Halt Detecting Flag When OSCBAKE This bit indicates the ...
Page 105
System Clock Select Operation Figure 5.2 shows the state transition of the system clock. Reset state On-chip oscillator: Halted External oscillator: Operated Note: * Conditions for the state transition are as follows: When the external oscillator halt is detected ...
Page 106
Section 5 Clock Pulse Generator LSI operates on on-chip oscillator clock Start (reset) Write 1 to PMRC0 in CKCSR Write 1 to PMRC1 in CKCSR Write 1 to OSCBAKE in CKCSR Clear CKSWIF in CKCSR to 0 Write 1 to ...
Page 107
LSI operates on on-chip oscillator clock Start (reset) Write 1 to PMRC0 in CKCSR Write 1 to PMRC1 in CKCSR Write 0 to CKSWIF in CKCSR Write 1 to OSCSEL in CKCSR Switched to external clock? (CKSTA in CKCSR is ...
Page 108
Section 5 Clock Pulse Generator Start (LSI operates on external clock) Write 0 to OSCBAKE in CKCSR Write 1 to CKSWIE in CKCSR if necessary Write 0 to OSCSEL in CKCSR LSI operates on on-chip oscillator clock When CKSWIE = ...
Page 109
Clock Switching Timing The timing for switching clocks are shown in figures 5.6 to 5.8. OSC RC OSCSEL PHISTOP (Internal signal) CKSTA On-chip oscillator clock operation Wait for external oscillation settling [Legend] OSC: External clock RC: On-chip oscillator clock ...
Page 110
Section 5 Clock Pulse Generator OSC RC OSCSEL PHISTOP (Internal signal) CKSTA CKSWIF External RC clock operation [Legend] OSC: External clock RC: On-chip oscillator clock : System clock OSCSEL: Bit 4 in CKCSR PHISTOP: System clock stop control signal CKSTA: ...
Page 111
OSC RC OSCHLT PHISTOP (Internal signal) CKSTA CKSWIF External clock operation [Legend] OSC: External clock RC: On-chip oscillator clock : System clock OSCHLT: Bit 1 in CKCSR PHISTOP: System clock stop control signal CKSTA: Bit 0 in CKCSR CKSWIF: Bit ...
Page 112
Section 5 Clock Pulse Generator 5.4 Trimming of On-Chip Oscillator Frequency Users can trim the on-chip oscillator clock, supplying the external reference pulses with the input capture function in internal timer Z. An example of trimming flow and a timing ...
Page 113
RC FTIOA0 input capture input Timer TCNT GRA_0 N GRC_0 Capture 1 Figure 5.10 Timing Chart of Trimming of On-Chip Oscillator Frequency The on-chip oscillator frequency is gained by the expression below. Since the input-capture ...
Page 114
Section 5 Clock Pulse Generator PC0/OSC1 PC1/OSC2/CLKOUT Figure 5.11 Example of Connection to Crystal Resonator PC0/OSC1 Figure 5.12 Equivalent Circuit of Crystal Resonator Table 5.1 Crystal Resonator Parameters Frequency (MHz (Max.) 120 S C (Max.) O 5.5.2 Connecting ...
Page 115
Inputting External Clock To use the external clock, input the external clock on pin OSC1. Figure 5.14 shows an example of connection. The duty cycle of the external clock signal must range from 45 to 55%. PC0/OSC1 PC1/OSC2/CLKOUT Figure ...
Page 116
Section 5 Clock Pulse Generator 5.6.1 Connecting 32.768-kHz Crystal Resonator Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystal resonator, as shown in figure 5.16. Figure 5.17 shows the equivalent circuit of the 32.768-kHz crystal ...
Page 117
Prescaler 5.7.1 Prescaler S Prescaler 13-bit counter using the system clock ( ) as its input clock. The outputs, which are divided clocks, are used as internal clocks by the on-chip peripheral modules. Prescaler S is ...
Page 118
Section 5 Clock Pulse Generator 5.8 Usage Notes 5.8.1 Note on Resonators Resonator characteristics are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Resonator circuit parameters will ...
Page 119
Section 6 Power-Down Modes This LSI has six modes of operation after a reset. These include a normal active mode and four power-down modes, in which power consumption is significantly reduced. Module standby mode reduces power consumption by selectively halting ...
Page 120
Section 6 Power-Down Modes 6.1 Register Descriptions The registers related to power-down modes are listed below. • System control register 1 (SYSCR1) • System control register 2 (SYSCR2) • Module standby control register 1 (MSTCR1) • Module standby control register ...
Page 121
Initial Bit Bit Name Value 6 STS2 0 5 STS1 0 4 STS0 0 3 NESEL 0 All 0 R/W Description R/W Standby Timer Select R/W These bits set the wait time from ...
Page 122
Section 6 Power-Down Modes Table 6.1 Operating Frequency and Waiting Time Bit Name STS2 STS1 STS0 Waiting Time 8,192 states 1 16,384 states 1 0 32,768 states 1 65,536 states 131,072 states 1 1,024 ...
Page 123
System Control Register 2 (SYSCR2) SYSCR2 controls the power-down modes, as well as SYSCR1. Initial Bit Bit Name Value 7 SMSEL 0 6 LSON 0 5 DTON 0 4 MA2 0 3 MA1 0 2 MA0 0 1 SA1 ...
Page 124
Section 6 Power-Down Modes 6.1.3 Module Standby Control Register 1 (MSTCR1) MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units. Initial Bit Bit Name Value MSTIIC 0 5 MSTS3 0 4 ...
Page 125
Module Standby Control Register 2 (MSTCR2) MSTCR2 allows the on-chip peripheral modules to enter a standby state in module units. Initial Bit Bit Name Value 7 MSTS3_2 0 All 0 4 MSTTB1 0 ...
Page 126
Section 6 Power-Down Modes 6.2 Mode Transitions and States of LSI Figure 6.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state by executing a SLEEP instruction. ...
Page 127
Table 6.2 Transition Mode after SLEEP Instruction Execution and Transition Mode due to Interrupt DTON SSBY SMSEL Don’t care. Note: * When a state transition is performed while ...
Page 128
Section 6 Power-Down Modes Table 6.3 Internal State in Each Operating Mode Function Active Mode External clock oscillator Functioning Subclock oscillator Functioning CPU Instructions Functioning operations Registers Functioning RAM Functioning IO ports Functioning External IRQ3 to IRQ0 Functioning interrupts WKP5 ...
Page 129
Sleep Mode In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock frequency set by the MA2, MA1, and MA0 bits in SYSCR2. CPU register contents are retained. When an interrupt is requested, ...
Page 130
Section 6 Power-Down Modes 6.2.3 Subsleep Mode In subsleep mode, operation of the CPU and on-chip peripheral modules other than RTC is halted. As long as a required voltage is applied, the contents of CPU registers, the on-chip RAM, and ...
Page 131
Operating Frequency in Active Mode Operation in active mode is clocked at the frequency designated by the MA2, MA1, and MA0 bits in SYSCR2. The operating frequency changes to the set frequency after SLEEP instruction execution. 6.4 Direct Transition ...
Page 132
Section 6 Power-Down Modes 6.4.2 Direct Transition from Subactive Mode to Active Mode The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (2). Direct transition ...
Page 133
The features of the 56- or 32-kbyte flash memory built into this LSI are summarized below. • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The 56-kbyte flash memory ...
Page 134
Section 7 ROM H'0000 Erase unit H'0080 1 kbyte H'0380 H'0400 Erase unit H'0480 1 kbyte H'0780 H'0800 Erase unit H'0880 1 kbyte H'0B80 H'0C00 Erase unit H'0C80 1 kbyte H'0F80 H'1000 Erase unit H'1080 28 kbytes H'7F80 H'8000 Erase ...
Page 135
Register Descriptions The flash memory has the following registers. • Flash memory control register 1 (FLMCR1) • Flash memory control register 2 (FLMCR2) • Erase block register 1 (EBR1) • Flash memory power control register (FLPWCR) • Flash memory ...
Page 136
Section 7 ROM Initial Bit Bit Name Value 7.2.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 ...
Page 137
Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 not set more than one bit at a time, as this will ...
Page 138
Section 7 ROM 7.2.4 Flash Memory Power Control Register (FLPWCR) FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. There are two modes: mode in which operation of the power ...
Page 139
On-Board Programming Modes There are two modes for programming/erasing of the flash memory; boot mode, which enables on- board programming/erasing, and programmer mode, in which programming/erasing is performed with a PROM programmer. On-board programming/erasing can also be performed in ...
Page 140
Section 7 ROM pulled up on the board if necessary. After the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. 4. After matching the bit rates, the chip transmits one ...
Page 141
Table 7.2 Boot Mode Operation Host Operation Processing Contents Continuously transmits data H'00 at specified bit rate. Transmits data H'55 when data H'00 is received error-free. Boot program erase error H'AA reception Transmits number of bytes (N) of programming control ...
Page 142
Section 7 ROM Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 19,200 bps MHz 9,600 bps MHz 4,800 ...
Page 143
Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the on- board programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: ...
Page 144
Section 7 ROM 8. The maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000. Write pulse application subroutine Apply Write Pulse WDT enable Set PSU bit in FLMCR1 Wait 50 µs Set P bit in ...
Page 145
Table 7.4 Reprogram Data Computation Table Program Data Verify Data Table 7.5 Additional-Program Data Computation Table Reprogram Data Verify Data Table 7.6 Programming Time ...
Page 146
Section 7 ROM 7.4.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 7.4 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only ...
Page 147
Set block start address as verify address H'FF dummy write to verify address Increment address No No Note: *The RTS instruction must not be used during a period between dummy writing of H' verify address and verify data ...
Page 148
Section 7 ROM 7.5 Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled ...
Page 149
The FLMCR1, FLMCR2, and EBR1 settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re- entered by re-setting the bit. ...
Page 150
Section 7 ROM Table 7.7 Flash Memory Operating States LSI Operating State Active mode Subactive mode Sleep mode Subsleep mode Standby mode Rev. 1.00 Sep. 16, 2005 Page 120 of 490 REJ09B0216-0100 Flash Memory Operating State PDWND = 0 (Initial ...
Page 151
This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte data and word data. Product Classification Flash memory version H8/36077F Note: ...
Page 152
Section 8 RAM Rev. 1.00 Sep. 16, 2005 Page 122 of 490 REJ09B0216-0100 ...
Page 153
This LSI has 47 general I/O ports and 8 general input-only ports. Port large current port, which can drive 20 mA (@V OL become an input port immediately after a reset. They can also be used as ...
Page 154
Section 9 I/O Ports 9.1.1 Port Mode Register 1 (PMR1) PMR1 switches the functions of pins in port 1 and port 2. Initial Bit Bit Name Value 7 IRQ3 0 6 IRQ2 0 5 IRQ1 0 4 IRQ0 0 3 ...
Page 155
Port Control Register 1 (PCR1) PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1. Initial Bit Bit Name Value 7 PCR17 0 6 PCR16 0 5 PCR15 0 4 PCR14 ...
Page 156
Section 9 I/O Ports 9.1.4 Port Pull-Up Control Register 1 (PUCR1) PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports. Initial Bit Bit Name Value 7 PUCR17 0 6 PUCR16 0 5 PUCR15 ...
Page 157
P16/IRQ2 pin Register PMR1 PCR1 Bit Name IRQ2 PCR16 Setting value [Legend] X: Don't care. P15/IRQ1/TMIB1 pin Register PMR1 PCR1 Bit Name IRQ1 PCR15 Setting value [Legend] X: Don't care. ...
Page 158
Section 9 I/O Ports P11/PWM pin Register PMR1 PCR1 Bit Name PWM PCR11 Setting value [Legend] X: Don't care. P10/TMOW pin Register PMR1 PCR1 Bit Name TMOW PCR10 Setting value ...
Page 159
Port 2 Port general I/O port also functioning as SCI3 I/O pins. Each pin of the port 2 is shown in figure 9.2. The register settings of PMR1and SCI3 have priority for functions of the pins ...
Page 160
Section 9 I/O Ports 9.2.2 Port Data Register 2 (PDR2) PDR2 is a general I/O port data register of port 2. Initial Bit Bit Name Value All 1 4 P24 0 3 P23 0 2 P22 ...
Page 161
Pin Functions The correspondence between the register specification and the port functions is shown below. P24 pin Register PCR2 Bit Name PCR24 Pin Function Setting Value 0 P24 input pin 1 P24 output pin P23 pin Register PCR2 Bit ...
Page 162
Section 9 I/O Ports P21/RXD pin Register SCR3 PCR2 Bit Name RE PCR21 Setting Value [Legend] X: Don't care. P20/SCK3 pin Register SCR3 Bit Name CKE1 CKE0 Setting Value ...
Page 163
Port 3 Port general I/O port. Each pin of the port 3 is shown in figure 9.3. Port 3 has the following registers. • Port control register 3 (PCR3) • Port data register 3 (PDR3) 9.3.1 ...
Page 164
Section 9 I/O Ports 9.3.2 Port Data Register 3 (PDR3) PDR3 is a general I/O port data register of port 3. Initial Bit Bit Name Value 7 P37 0 6 P36 0 5 P35 0 4 P34 0 3 P33 ...
Page 165
P35 pin Register PCR3 Bit Name PCR35 Pin Function Setting Value 0 P35 input pin 1 P35 output pin P34 pin Register PCR3 Bit Name PCR34 Pin Function Setting Value 0 P34 input pin 1 P34 output pin P33 pin ...
Page 166
Section 9 I/O Ports P31 pin Register PCR3 Bit Name PCR31 Pin Function Setting Value 0 P31 input pin 1 P31 output pin P30 pin Register PCR3 Bit Name PCR30 Pin Function Setting Value 0 P30 input pin 1 P30 ...
Page 167
Port 5 Port general I/O port also functioning pin, and wakeup interrupt input pin. Each pin of the port 5 is shown in figure 9.4. The register 2 setting of the I C ...
Page 168
Section 9 I/O Ports 9.4.1 Port Mode Register 5 (PMR5) PMR5 switches the functions of pins in port 5. Initial Bit Bit Name Value 7 POF57 0 6 POF56 0 5 WKP5 0 4 WKP4 0 3 WKP3 0 2 ...
Page 169
Port Control Register 5 (PCR5) PCR5 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 5. Initial Bit Bit Name Value 7 PCR57 0 6 PCR56 0 5 PCR55 0 4 PCR54 ...
Page 170
Section 9 I/O Ports 9.4.4 Port Pull-Up Control Register 5 (PUCR5) PUCR5 controls the pull-up MOS in bit units of the pins set as the input ports. Initial Bit Bit Name Value All 0 5 PUCR55 0 ...
Page 171
P56/SDA pin Register ICCR1 PCR5 Bit Name ICE PCR56 Setting Value [Legend] X: Don't care. SDA performs the NMOS open-drain output, that enables a direct bus drive. P55/WKP5/ADTRG pin Register PMR5 PCR5 Bit Name WKP5 ...
Page 172
Section 9 I/O Ports P53/WKP3 pin Register PMR5 PCR5 Bit Name WKP3 PCR53 Setting Value [Legend] X: Don't care. P52/WKP2 pin Register PMR5 PCR5 Bit Name WKP2 PCR52 Setting Value ...
Page 173
Port 6 Port general I/O port also functioning as a timer Z I/O pin. Each pin of the port 6 is shown in figure 9.5. The register setting of the timer Z has priority for functions ...
Page 174
Section 9 I/O Ports 9.5.2 Port Data Register 6 (PDR6) PDR6 is a general I/O port data register of port 6. Initial Bit Bit Name Value 7 P67 0 6 P66 0 5 P65 0 4 P64 0 3 P63 ...
Page 175
P66/FTIOC1 pin Register TOER TFCR CMD1 and Bit Name EC1 CMD0 Setting Value Other than 00 [Legend] X: Don't care. P65/FTIOB1 pin Register TOER TFCR CMD1 to Bit Name EB1 CMD0 Setting Value ...
Page 176
Section 9 I/O Ports P64/FTIOA1 pin Register TOER TFCR CMD1 to Bit Name EB1 CMD0 Setting Value [Legend] X: Don't care. P63/FTIOD0 pin Register TOER TFCR CMD1 to Bit Name ED0 CMD0 Setting Value 1 00 ...
Page 177
P61/FTIOB0 pin Register TOER TFCR CMD1 to Bit Name EB0 CMD0 Setting Value Other than 00 [Legend] X: Don't care. P60/FTIOA0 pin Register TOER TFCR CMD1 to Bit Name EA0 CMD0 Setting Value ...
Page 178
Section 9 I/O Ports 9.6 Port 7 Port general I/O port also functioning as a timer V I/O pin and SCI3_2 I/O pin. Each pin of the port 7 is shown in figure 9.6. The register settings ...
Page 179
Port Data Register 7 (PDR7) PDR7 is a general I/O port data register of port 7. Initial Bit Bit Name Value P76 0 5 P75 0 4 P74 0 P72 0 ...
Page 180
Section 9 I/O Ports P74/TMRIV pin Register PCR7 Bit Name PCR74 Pin Function Setting Value 0 P74 input/TMRIV input pin 1 P74 output/TMRIV input pin P72/TXD_2 pin Register PMR1 PCR7 Bit Name TXD2 PCR72 Setting Value ...
Page 181
Port 8 Port general I/O port. Each pin of the port 8 is shown in figure 9.7. Port 8 has the following registers. • Port control register 8 (PCR8) • Port data register 8 (PDR8) 9.7.1 ...
Page 182
Section 9 I/O Ports 9.7.3 Pin Functions The correspondence between the register specification and the port functions is shown below. P87 pin Register PCR8 Bit Name PCR87 Pin Function Setting Value 0 P87 input pin 1 P87 output pin P86 ...
Page 183
Port B Port input port also functioning as an A/D converter analog input pin. Each pin of the port B is shown in figure 9.8. Port B has the following register. • Port data register B ...
Page 184
Section 9 I/O Ports 9.8.2 Pin Functions The correspondence between the register specification and the port functions is shown below. PB0/AN0 pin Register Bit Name SCAN Setting Value 0 1 Other than above [Legend] X: Don't care. PB1/AN1 pin Register ...
Page 185
PB3/AN3 pin Register Bit Name SCAN Setting Value 0 1 Other than above [Legend] X: Don't care. PB4/AN4 pin Register Bit Name SCAN Setting Value 0 1 Other than above [Legend] X: Don't care. PB5/AN5 pin Register Bit Name SCAN ...
Page 186
Section 9 I/O Ports PB6/AN6/ExtD pin Register Bit Name SCAN Setting Value Other than above [Legend] X: Don't care. PB7/AN7/ExtU pin Register Bit Name SCAN Setting Value Other than above [Legend] X: ...
Page 187
Port C Port general I/O port also functioning as an external oscillation pin and clock output pin. Each pin of the port C is shown in figure 9.9. The register setting of CKCSR has priority for ...
Page 188
Section 9 I/O Ports 9.9.2 Port Data Register C (PDRC) PDRC is a general I/O port data register of port C. Initial Bit Bit Name Value PC1 0 0 PC0 0 9.9.3 Pin Functions ...
Page 189
Section 10 Realtime Clock (RTC) The realtime clock (RTC timer used to count time ranging from a second to a week. Figure 10.1 shows the block diagram of the RTC. 10.1 Features • Counts seconds, minutes, hours, and ...
Page 190
Section 10 Realtime Clock (RTC) 10.2 Input/Output Pin Table 10.1 shows the RTC input/output pin. Table 10.1 Pin Configuration Name Clock output Rev. 1.00 Sep. 16, 2005 Page 160 of 490 REJ09B0216-0100 Abbreviation I/O Function TMOW Output RTC divided clock ...
Page 191
Register Descriptions The RTC has the following registers. • Second data register/free running counter data register (RSECDR) • Minute data register (RMINDR) • Hour data register (RHRDR) • Day-of-week data register (RWKDR) • RTC control register 1 (RTCCR1) • ...
Page 192
Section 10 Realtime Clock (RTC) 10.3.2 Minute Data Register (RMINDR) RMINDR counts the BCD-coded minute value on the carry generated once per minute by the RSECDR counting. The setting range is decimal 00 to 59. Initial Bit Bit Name Value ...
Page 193
Hour Data Register (RHRDR) RHRDR counts the BCD-coded hour value on the carry generated once per hour by RMINDR. The setting range is either decimal the selection of the 12/24 bit ...
Page 194
Section 10 Realtime Clock (RTC) 10.3.4 Day-of-Week Data Register (RWKDR) RWKDR counts the BCD-coded day-of-week value on the carry generated once per day by RHRDR. The setting range is decimal using bits WK2 to WK0. Initial Bit ...
Page 195
RTC Control Register 1 (RTCCR1) RTCCR1 controls start/stop and reset of the clock timer. For the definition of time expression, see figure 10.2. Initial Bit Bit Name Value 7 RUN — 6 12/24 — — 4 RST ...
Page 196
Section 10 Realtime Clock (RTC) 10.3.6 RTC Control Register 2 (RTCCR2) RTCCR2 controls RTC periodic interrupts of weeks, days, hours, minutes, and seconds. Enabling interrupts of weeks, days, hours, minutes, and seconds sets the IRRTA flag the ...
Page 197
Clock Source Select Register (RTCCSR) RTCCSR selects clock source. A free running counter controls start/stop of counter operation by the RUN bit in RTCCR1. When a clock other than 32.768 kHz is selected, the RTC is disabled and operates ...
Page 198
Section 10 Realtime Clock (RTC) 10.4 Operation 10.4.1 Initial Settings of Registers after Power-On The RTC registers that store second, minute, hour, and day-of week data are not reset by a RES input. Therefore, all registers must be set to ...
Page 199
Data Reading Procedure When the seconds, minutes, hours, or day-of-week datum is updated while time data is being read, the data obtained may not be correct, and so the time data must be read again. Figure 10.4 shows an ...
Page 200
Section 10 Realtime Clock (RTC) 10.5 Interrupt Sources There are five kinds of RTC interrupts: week interrupts, day interrupts, hour interrupts, minute interrupts, and second interrupts. When using an interrupt, initiate the RTC last after other registers are set. Do ...