HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 381

16BIT MCU FLASH 56K, SMD, LQFP64

HD64F36077GHV

Manufacturer Part Number
HD64F36077GHV
Description
16BIT MCU FLASH 56K, SMD, LQFP64
Manufacturer
Renesas Electronics America
Datasheet

Specifications of HD64F36077GHV

No. Of I/o's
47
Ram Memory Size
4KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Supply Voltage Range
4.5V
Core Size
16bit
Program Memory Size
56KB
Oscillator Type
External Only
Controller Family/series
H8/300H
Peripherals
ADC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F36077GHV
Manufacturer:
RENESAS
Quantity:
340
Part Number:
HD64F36077GHV
Manufacturer:
Renesas
Quantity:
200
Part Number:
HD64F36077GHV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
No
No
No
Clear ACKBT in ICIER to 0
Clear RCVD in ICCR1 to 0
Set ACKBT in ICIER to 1
Clear MST in ICCR1 to 0
Clear TRS in ICCR1 to 0
Set RCVD in ICCR1 to 1
Clear STOP in ICSR.
Dummy-read ICDRR
Read RDRF in ICSR
Read RDRF in ICSR
Clear TEND in ICSR
Clear TDRE in ICSR
Read STOP in ICSR
Mater receive mode
Write 0 to BBSY
Read ICDRR
Read ICDRR
Read ICDRR
Last receive
RDRF=1 ?
RDRF=1 ?
STOP=1 ?
and SCP
End
- 1?
Figure 17.18 Sample Flowchart for Master Receive Mode
Yes
Yes
Yes
No
Yes
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Clear the STOP flag.
[11] Issue the stop condition.
[12] Wait for the creation of stop condition.
[13] Read the last byte of receive data.
[14] Clear RCVD.
[15] Set slave receive mode.
Note: Do not activate an interrupt during the execution of steps [1] to [3].
Supplementary explanation: When one byte is received, steps [2] to [6] are
Clear TEND, select master receive mode, and then clear TDRE.*
Set acknowledge to the transmit device.*
Dummy-read ICDDR.*
Wait for 1 byte to be received
Check whether it is the (last receive - 1).
Read the receive data last.
Set acknowledge of the final byte. Disable continuous reception (RCVD = 1).
Read the (final byte - 1) of receive data.
Wait for the last byte to be receive.
skipped after step [1], before jumping to step [7].
The step [8] is dummy-read in ICDRR.
Rev. 1.00 Sep. 16, 2005 Page 351 of 490
Section 17 I
2
C Bus Interface 2 (IIC2)
REJ09B0216-0100

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