HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 334

• Manufacturer Part Number: HD64F36077GHV
• Description: 16BIT MCU FLASH 56K, SMD, LQFP64
• Manufacturer: Renesas Electronics America

Specifications of HD64F36077GHV

• No. Of I/o's: 47
• Ram Memory Size: 4KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 4.5V
• Core Size: 16bit
• Program Memory Size: 56KB
• Oscillator Type: External Only
• Controller Family/series: H8/300H
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 16 Serial Communication Interface 3 (SCI3)
16.5.3
Figure 16.10 shows an example of SCI3 operation for transmission in clock synchronous mode.
In serial transmission, the SCI3 operates as described below.
1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI3 recognizes that data
2. The SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR3 is set to 1 at
3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock
4. The SCI3 checks the TDRE flag at the timing for sending the MSB (bit 7).
5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains
7. The SCK3 pin is fixed high at the end of transmission.
Figure 16.11 shows a sample flow chart for serial data transmission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (OER, FER, or PER) is set to 1.
Make sure that the receive error flags are cleared to 0 before starting transmission.
Rev. 1.00 Sep. 16, 2005 Page 304 of 490
REJ09B0216-0100
has been written to TDR, and transfers the data from TDR to TSR.
this time, a transmit data empty interrupt (TXI) is generated.
mode has been specified, and synchronized with the input clock when use of an external clock
has been specified. Serial data is transmitted sequentially from the LSB (bit 0), from the TxD
pin.
of the next frame is started.
the output state of the last bit. If the TEIE bit in SCR3 is set to 1 at this time, a TEI interrupt
request is generated.
TDRE
TEND
LSI
operation
User
processing
Serial
clock
Serial
data
Figure 16.10 Example of SCI3 Transmission in Clock Synchronous Mode
Serial Data Transmission
TXI interrupt
request
generated
Bit 0
Bit 1
TDRE flag
cleared
to 0
Data written
to TDR
1 frame
TXI interrupt request generated
Bit 7
Bit 0
Bit 1
1 frame
Bit 6
TEI interrupt request
generated
Bit 7