DSP56309EVM Freescale Semiconductor, DSP56309EVM Datasheet - Page 186

• Manufacturer Part Number: DSP56309EVM
• Description: KIT EVALUATION FOR XC56309
• Manufacturer: Freescale Semiconductor
• Type: DSPr

Specifications of DSP56309EVM

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Description/function: Audio DSPs
• Product: Audio Modules
• For Use With/related Products: DSP56309
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Serial Communication Interface (SCI)
The SCI clock determines the data transmission (baud) rate and can also establish a periodic
interrupt that can act as an event timer or be used in any other timing function. Bits CD11– CD0,
SCP, and SCR[STIR] work together to determine the time base. If SCR[TMIE] = 1 when the
periodic time-out occurs, the SCI timer interrupt is recognized and pending. The SCI timer
interrupt is automatically cleared when the interrupt is serviced. This interrupt occurs every time
the periodic timer times out.
Figure 8-5 shows the block diagram of the internal clock generation circuitry with the formula to
compute the bit rate when the internal clock is used.
As noted in Section 8.6.1, the SCI can be configured to operate in a single Synchronous mode or
one of five Asynchronous modes. Synchronous mode requires that the TX and RX clocks use the
same source, but that source may be the internal SCI clock if the SCI is configured as a master
device or an external clock if the SCI is configured as a slave device. Asynchronous modes may
use clocks from the same source (internal or external) or different sources for the TX clock and
the RX clock.
For synchronous operation, the SCI uses a clock that is equal to the two times the desired bit rate
(designated as the 2
source for both the TX and RX clock. The internal clock is used if the SCI is the master device
8-18
STIR
F
bps = 64 × (7(SCP) + 1) × CD + 1)
where:
core
SCP = 0 or 1
CD = $000 to $FFF
Divide
By 2
Timer
Interrupt
(STMINT)
Fcore
×
Divide
by 16
clock) for both internal and external clock sources. It must use the same
Figure 8-5. SCI Baud Rate Generator
12-bit Counter
CD[11–0]
DSP56309 User’s Manual, Rev. 1
Uses Divide by 16 for
Uses Divide by 2 for
SCI Core Logic
Asynchronous
Synchronous
Prescaler:
Divide by
1 or 8
SCP
SCKP
COD
Divide
Internal Clock
Freescale Semiconductor
By 2
Divide by 1 or 16
If Asynchronous
If Synchronous
SCKP = 0 +
SCKP = 1
Divide By 2
SCLK
-