DSP56309EVM Freescale Semiconductor, DSP56309EVM Datasheet - Page 148

• Manufacturer Part Number: DSP56309EVM
• Description: KIT EVALUATION FOR XC56309
• Manufacturer: Freescale Semiconductor
• Type: DSPr

Specifications of DSP56309EVM

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Description/function: Audio DSPs
• Product: Audio Modules
• For Use With/related Products: DSP56309
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Enhanced Synchronous Serial Interface (ESSI)
7-16
Sync:
Async:
Sync:
Async:
RX Word
These signals are
identical in sync mode.
TX Word
TX 1, or
Flag0
RX clk
TX/RX clk
TX clk
Clock
Clock
F
SCn0
CORE
SCKn
Figure 7-4. ESSI Frame Sync Generator Functional Block Diagram
CRA(DC4–0)
CRA(DC4:0)
CRB(SCD0)
CRB(SCKD)
Figure 7-3. ESSI Clock Generator Functional Block Diagram
/1 to /32
CRB(FSL[1–0])
/1 to /32
Transmit
Receive
Control
Control
0
0
Logic
Logic
/2
CRB(FSR)
31
31
CRB(TE1)
TX 1
(Sync Mode)
Frame Sync
Frame Sync
Transmit
Receive
or
CRA(PSR)
(Opposite
from SSI)
SYN = 0
CRB(SYN) = 0
/1 or /8
Flag0 Out
CRB(OF0)
1
CRB(SYN) = 1
Sync-
Type
Sync
Type
DSP56309 User’s Manual, Rev. 1
0
SYN =
CRB(FSL1)
CRB(FSR)
(Sync Mode)
Internal Rx Frame Sync
SSISR(IF0)
Internal Bit Clock
SCD0 = 1
CRA(PM7:0)
Flag0 In
/1 to /256
CRB(SCD1) = 1
0
Internal TX Frame Sync
SCD1 =
SCD0 = 0
255
(Sync Mode)
SSISR(IF1)
Flag1 In
SYN = 0
SYN = 1
RCLOCK
TCLOCK
• F
• ESSI internal clock range:
• ‘n’ in signal name is ESSI # (0 or 1)
clock frequency.
min = F
max = F
CORE
SYN = 1
SYN = 0
CRB(TE2)
TX 2,
RX Shift Register
is the DSP56300 core internal
OSC
OSC
TX Shift Register
0
/8, /12, /16, /24,
0
CRA(WL2–0)
CRA(WL2–0)
/8, /12, /16, /24,
/4096
/4
1
1
(Sync Mode)
Flag1 Out,
CRB(OF1)
CRB(SCD1)
2
2
CRB(SCD2)
3 4,5
3 4,5
Freescale Semiconductor
or drive enb.
CRA(SSC1)
Sync:
Async:
TX 2 Flag1,
or drive enb.
RX F .S.
SCn1
SCn2
Sync:
Async:
TX/RX F.S.
TX F.S.
RX
Word
Clock
TX
Word
Clock