DSP56309EVM Freescale Semiconductor, DSP56309EVM Datasheet - Page 166

• Manufacturer Part Number: DSP56309EVM
• Description: KIT EVALUATION FOR XC56309
• Manufacturer: Freescale Semiconductor
• Type: DSPr

Specifications of DSP56309EVM

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Description/function: Audio DSPs
• Product: Audio Modules
• For Use With/related Products: DSP56309
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Enhanced Synchronous Serial Interface (ESSI)
7.6.2 Port Direction Registers (PRRC and PRRD)
The read/write PRRC and PRRD control the data direction of the ESSI0 and ESSI1 GPIO signals
when they are enabled by the associated Port Control Register (PCRC or PCRD, respectively).
When PRRC[i] or PRRD[i] is set, the corresponding signal is an output (GPO) signal. When
PRRC[i] or PRRD[i] is cleared, the corresponding signal is an input (GPI) signal. Either a
hardware
Table 7-6 summarizes the ESSI port signal configurations.
7.6.3 Port Data Registers (PDRC and PDRD)
Bits 5–0 of the read/write PDRs write data to or read data from the associated ESSI GPIO signal
lines if they are configured as GPIO signals. If a port signal PC[i] or PD[i] is configured as an
input (GPI), the corresponding PDRC[i] pr PDRD[i] bit reflects the value present on the input
7-34
Note:
Note:
X: The signal setting is irrelevant to the Port Signal[i] function.
23
11
23
11
PCRC/PCRD[i]
For Px[5–0], a 0 selects Pxn as the signal and a 1 selects the specified ESSI signal. For ESSI0, the GPIO signals are
PC[5–0] and the ESSI signals are STD0, SRD0, SCK0, and SC0[2–0]. For ESSI1, the GPIO signals are PD[5–0] and
the ESSI signals are STD1, SRD1, SCK1, and SC1[2–0].
For bits 5–0, a 0 configures PRxn as a GPI and a 1 configures PRxn as a GPO. For ESSI0, the GPIO signals are
PC[5–0]. For ESSI1, the GPIO signals are PD[5–0]. The corresponding direction bits for Port C GPIOs are PRC[5–0].
The corresponding direction bits for Port D GPIOs are PRD[5–0].
Figure 7-19. Port Direction Registers (PRRC X:$FFFFBE) (PRRD X: $FFFFAE)
= Reserved. Read as zero. Write with zero for future compatibility.
= Reserved. Read as zero. Write with zero for future compatibility.
Figure 7-18. Port Control Registers (PCRC X:$FFFFBF) (PCRD X:$FFFAF)
RESET
1
0
0
22
10
22
10
signal or a software RESET instruction clears all PRRC and PRRD bits.
21
21
9
9
Table 7-6. ESSI Port Signal Configurations
PRRC/PRRD[i]
20
20
8
8
X
0
1
DSP56309 User’s Manual, Rev. 1
19
19
7
7
18
18
6
6
PCx5
PRx5
17
17
5
5
PRx4
PCx4
16
16
4
4
Port Signal[i] Function
Port C/Port D GPO
Port C/Port D GPI
ESSI0/ESSI1
PCx3
PRx3
15
15
3
3
PCx2
PRx2
14
14
2
2
Freescale Semiconductor
PCx1
PRx1
13
13
1
1
PRx0
PCx0
12
12
0
0