C8051F930-TB Silicon Laboratories Inc, C8051F930-TB Datasheet - Page 73

• Manufacturer Part Number: C8051F930-TB
• Description: BOARD TARGET/PROTO W/C8051F930
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F930-TB

• Contents: Board
• Processor To Be Evaluated: C8051F930
• Processor Series: C8051F9xx
• Data Bus Width: 8 bit
• Interface Type: I2C, UART, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 0.9 V to 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F930
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1472

SFR Definition 5.2. ADC0CF: ADC0 Configuration
SFR Page = 0x0; SFR Address = 0xBC
Name
Reset
Type
Bit
7:3
2
1
0
Bit
AD0SC[4:0]
AMP0GN
AD08BE
AD0TM
Name
7
1
ADC0 SAR Conversion Clock Divider.
SAR Conversion clock is derived from FCLK by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC[4:0]. SAR Conversion clock
requirements are given in Table 4.9.
BURSTEN = 0: FCLK is the current system clock.
BURSTEN = 1: FCLK is the 20 MHz low power oscillator, independent of the system
clock.
ADC0 8-Bit Mode Enable.
0: ADC0 operates in 10-bit mode (normal operation).
1: ADC0 operates in 8-bit mode.
ADC0 Track Mode.
Selects between Normal or Delayed Tracking Modes.
0: Normal Track Mode: When ADC0 is enabled, conversion begins immediately following the
start-of-conversion signal.
1: Delayed Track Mode: When ADC0 is enabled, conversion begins 3 SAR clock cycles fol-
lowing the start-of-conversion signal. The ADC is allowed to track during this time.
ADC0 Gain Control.
0: The on-chip PGA gain is 0.5.
1: The on-chip PGA gain is 1.
6
1
AD0SC
CLK
*Round the result up.
AD0SC[4:0]
SAR
R/W
=
5
1
=
------------------- - 1
CLK
FCLK
----------------------------
AD0SC
FCLK
SAR
or
Rev. 1.1
4
1
–
+
1
*
C8051F93x-C8051F92x
Function
3
1
AD08BE
R/W
2
0
AD0TM
R/W
1
0
AMP0GN
R/W
0
0
73