C8051F930-TB Silicon Laboratories Inc, C8051F930-TB Datasheet - Page 37
![BOARD TARGET/PROTO W/C8051F930](/photos/9/25/92560/c8051f930-tb_sml.jpg)
C8051F930-TB
Manufacturer Part Number
C8051F930-TB
Description
BOARD TARGET/PROTO W/C8051F930
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F930-TB
Contents
Board
Processor To Be Evaluated
C8051F930
Processor Series
C8051F9xx
Data Bus Width
8 bit
Interface Type
I2C, UART, SPI
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
0.9 V to 3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F930
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1472
- Current page: 37 of 324
- Download datasheet (3Mb)
Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
4. A 3 x 3 array of 1.0 mm square openings on 1.2 mm pitch should be used for the
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
be used to assure good solder paste release.
center ground pad.
for Small Body Components.
Dimension
C1
C2
X1
X2
Y1
Y2
E
Table 3.3. PCB Land Pattern
Rev. 1.1
4.80
4.80
0.20
3.20
0.75
3.20
MIN
C8051F93x-C8051F92x
0.50 BSC
4.90
4.90
0.30
3.40
0.85
3.40
MAX
37
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