C8051F930-TB Silicon Laboratories Inc, C8051F930-TB Datasheet - Page 174
![BOARD TARGET/PROTO W/C8051F930](/photos/9/25/92560/c8051f930-tb_sml.jpg)
C8051F930-TB
Manufacturer Part Number
C8051F930-TB
Description
BOARD TARGET/PROTO W/C8051F930
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F930-TB
Contents
Board
Processor To Be Evaluated
C8051F930
Processor Series
C8051F9xx
Data Bus Width
8 bit
Interface Type
I2C, UART, SPI
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
0.9 V to 3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F930
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1472
- Current page: 174 of 324
- Download datasheet (3Mb)
C8051F93x-C8051F92x
16.4. Enabling the DC-DC Converter
On power-on reset, the state of the DCEN pin is sampled to determine if the device will power up in one-
cell or two-cell mode. In two-cell mode, the dc-dc converter always remains disabled. In one-cell mode, the
dc-dc converter remains disabled in Sleep Mode, and enabled in all other power modes. See Section
“14. Power Management” on page 146 for complete details on available power modes.
The dc-dc converter is enabled (one-cell mode) in hardware by placing a 0.68 µH inductor between DCEN
and VBAT. The dc-dc converter is disabled (two-cell mode) by shorting DCEN directly to GND. The DCEN
pin should never be left floating. Note that the device can only switch between one-cell and two-cell mode
during a power-on reset. See Section “18. Reset Sources” on page 173 for more information regarding
reset behavior.
Figure 16.2 shows the two dc-dc converter configuration options.
When the dc-dc converter “Enabled” configuration (one-cell mode) is chosen, the following guidelines
apply:
•
•
•
•
•
174
DC-DC Converter
Enabled
0.9 to 1.8 V
Supply Voltage
(one-cell mode)
DC-DC Converter
Disabled
1.8 to 3.6 V
Supply Voltage
(two-cell mode)
In most cases, the GND/DC– pin should not be externally connected to GND.
The 0.68 µH inductor should be placed as close as possible to the DCEN pin for maximum efficiency.
The 4.7 µF capacitor should be placed as close as possible to the inductor.
The current loop including GND, the 4.7 µF capacitor, the 0.68 µH inductor and the DCEN pin should
be made as short as possible.
The PCB traces connecting VDD/DC+ to the output capacitor and the output capacitor to GND/DC–
should be as short and as thick as possible in order to minimize parasitic inductance.
Figure 16.2. DC-DC Converter Configuration Options
VBAT
VBAT
Rev. 1.1
4.7 uF
GND
GND
0.68 uH
DCEN
DCEN
VDD/DC+
VDD/DC+
GND/DC-
GND/DC-
1 uF
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