DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 35

• Manufacturer Part Number: DK-DEV-2AGX125N
• Description: KIT DEV ARRIA II GX FPGA 2AGX125
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX125N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX125EF35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2600

Chapter 6: Board Test System
Using the Board Test System
Figure 6–8. The HSMC Tab
February 2011 Altera Corporation
The HSMC Tab
■
■
W/R Control
This control specifies the type of transactions to analyze. The following transaction
types are available for analysis:
■
■
■
The HSMC tab allows you to perform loopback tests on the HSMC port.
shows the HSMC tab.
Memory—Selects a generic data pattern stored in the on chip memory of the
Arria II GX device.
Math—Selects data generated from a simple math function within the FPGA
fabric.
Write/Read—Selects read and write transactions for analysis.
Read Only—Selects read transactions for analysis.
Write Only—Selects write transactions for analysis.
Arria II GX FPGA Development Kit User Guide
Figure 6–8
6–15