DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 32

• Manufacturer Part Number: DK-DEV-2AGX125N
• Description: KIT DEV ARRIA II GX FPGA 2AGX125
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX125N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX125EF35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2600

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Arria II GX FPGA Development Kit User Guide
Frequency rates for production silicon speed grade C4N only.
The following sections describe the controls on the DDR3 tab.
Start
This control initiates DDR3 memory transaction performance analysis.
Stop
This control terminates transaction performance analysis.
Performance Indicators
These controls display current transaction performance analysis information collected
since you last pressed Start:
■
■
Error Control
These controls display data errors detected during analysis and allow you to insert
errors:
■
■
■
■
Number of Addresses to Write/Read
This control determines the number of addresses to use in each iteration of reads and
writes. Valid values range from 8 to 67108864.
■
■
Data Type
This control specifies the type of data contained in the transactions. The following
data types are available for analysis:
■
Write, Read, and Total performance bars—Show the percentage of maximum
theoretical data rate that the requested transactions are able to achieve.
Write (MBytes/s), Read (MBytes/s), and Total (MBytes/s)—Show the number of
bytes of data analyzed per second. The data bus is 16 bits wide and the frequency
is 400 MHz double data rate (800 Mbps per pin), equating to a theoretical
maximum bandwidth of 1600 MBps.
Detected Errors—Displays the number of data errors detected in the hardware.
Inserted Errors—Displays the number of errors inserted into the transaction
stream.
Insert Error—Inserts a one-word error into the transaction stream each time you
click the button. Insert Error is only enabled during transaction performance
analysis.
Clear—Resets the Detected errors and Inserted errors counters to zeros.
The minimum range, when on the slider is at the Min position on the left, is the
maximum PHY burst of 8.
The maximum range, when the slider is at the Max position on the right, fills the
full address space of the DDR3.
PRBS—Selects pseudo-random bit sequences.
February 2011 Altera Corporation
Chapter 6: Board Test System
Using the Board Test System
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