DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 23

• Manufacturer Part Number: DK-DEV-2AGX125N
• Description: KIT DEV ARRIA II GX FPGA 2AGX125
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX125N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX125EF35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2600

Chapter 6: Board Test System
Preparing the Board
Preparing the Board
Running the Board Test System
February 2011 Altera Corporation
1
1
1
The Board Test System and Power Monitor share the JTAG bus with other
applications like the Nios II debugger and the SignalTap
Analyzer. Because the Quartus II programmer uses most of the bandwidth of the
JTAG bus, other applications using the JTAG bus might time out. Be sure to close the
other applications before attempting to reconfigure the FPGA using the Quartus II
Programmer.
With the power to the board off, perform the following steps:
1. Connect the USB cable to the board.
2. Verify the settings for the board settings DIP switch bank (SW4) match
3. Set the USER_LOAD switch (SW4.4) to the on position.
4. Verify the settings for the JTAG jumper block (J9) match
5. Turn the power to the board on. The board loads the design stored in the user
To run the application, navigate to the <install
dir>\kits\arriaIIGX_2agx125_fpga\examples\board_test_system directory and run
the BoardTestSystem.exe application.
On Windows, click Start > All Programs > Altera > Arria II GX FPGA Development
Kit <version> > Board Test System to run the application.
A GUI appears, displaying the application tab that corresponds to the design running
in the FPGA. The Arria II GX FPGA development board’s flash memory ships
preconfigured with the design that corresponds to the Config, GPIO, and SSRAM,
and Flash tabs.
If you power up your board with the USER_LOAD switch (SW4.4) in the off position,
or if you load your own design into the FPGA with the Quartus II Programmer, you
receive a message prompting you to configure your board with a valid Board Test
System design. Refer to
your board.
on page
These settings determine the devices to include in the JTAG chain.
f
hardware 1 portion of flash memory into the FPGA. If your board is still in the
factory configuration or if you have downloaded a newer version of the Board Test
System to flash memory through the Board Update Portal, the design loads the
GPIO, SRAM, and flash memory tests.
c
For more information about the board’s DIP switch and jumper settings,
refer to the
To ensure operating stability, keep the USB cable connected and the board
powered on when running the demonstration application. The application
cannot run correctly unless the USB cable is attached and the board is on.
4–3.
Arria II GX FPGA Development Board Reference
“The Configure Menu”
for information about configuring
Arria II GX FPGA Development Kit User Guide
®
II Embedded Logic
Table 4–3 on page
Manual.
Table 4–2
4–3.
6–3