DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 34
![KIT DEV ARRIA II GX FPGA 2AGX125](/photos/28/41/284154/dk-dev-2agx125n_sml.jpg)
DK-DEV-2AGX125N
Manufacturer Part Number
DK-DEV-2AGX125N
Description
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer
Altera
Series
Arria II GXr
Type
FPGAr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.DK-DEV-2AGX125N.pdf
(48 pages)
3.DK-DEV-2AGX125N.pdf
(64 pages)
Specifications of DK-DEV-2AGX125N
Contents
Board, Cables, CD, DVD, Power Supply
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Arria
Silicon Core Number
EP2
Silicon Family Name
Arria II GX
Rohs Compliant
Yes
For Use With/related Products
EP2AGX125EF35
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2600
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-2AGX125N
Manufacturer:
Altera
Quantity:
135
6–14
1
Arria II GX FPGA Development Kit User Guide
Frequency rates for production silicon speed grade C4N only.
The following sections describe the controls on the DDR2 tab.
Start
This control initiates DDR2 memory transaction performance analysis.
Stop
This control terminates transaction performance analysis.
Performance Indicators
These controls display current transaction performance analysis information collected
since you last clicked Start:
■
■
Error Control
This control displays data errors detected during analysis and allows you to insert
errors:
■
■
■
■
Number of Addresses to Write/Read
This control determines the number of addresses to use in each iteration of reads and
writes. Valid values range from 8 to 134217728.
■
■
Data Type
This control specifies the type of data contained in the transactions. The following
data types are available for analysis:
■
Write, Read, and Total performance bars—Show the percentage of maximum
theoretical data rate that the requested transactions are able to achieve.
Write (MBytes/s), Read (MBytes/s), and Total (MBytes/s)—Show the number of
bytes of data analyzed per second. The data bus is 64 bits wide and the frequency
is 333 MHz double data rate (667 Mbps per pin), equating to a theoretical
maximum bandwidth of 5333 MBps.
Detected Errors—Displays the number of data errors detected in the hardware.
Inserted Errors—Displays the number of errors inserted into the transaction
stream.
Insert Error—Inserts a one-word error into the transaction stream each time you
click the button. Insert Error is only enabled during transaction performance
analysis.
Clear—Resets the Detected errors and Inserted errors counters to zeros.
The minimum range, when on the slider is at the Min position on the left, is the
maximum PHY burst of 8.
The maximum range, when the slider is at the Max position on the right, fills the
full address space of the DDR2 SODIMM.
PRBS—Selects pseudo-random bit sequences.
February 2011 Altera Corporation
Chapter 6: Board Test System
Using the Board Test System
1