DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 26
![KIT DEV ARRIA II GX FPGA 2AGX125](/photos/28/41/284154/dk-dev-2agx125n_sml.jpg)
DK-DEV-2AGX125N
Manufacturer Part Number
DK-DEV-2AGX125N
Description
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer
Altera
Series
Arria II GXr
Type
FPGAr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.DK-DEV-2AGX125N.pdf
(48 pages)
3.DK-DEV-2AGX125N.pdf
(64 pages)
Specifications of DK-DEV-2AGX125N
Contents
Board, Cables, CD, DVD, Power Supply
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Arria
Silicon Core Number
EP2
Silicon Family Name
Arria II GX
Rohs Compliant
Yes
For Use With/related Products
EP2AGX125EF35
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2600
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-2AGX125N
Manufacturer:
Altera
Quantity:
135
6–6
Arria II GX FPGA Development Kit User Guide
1
1
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■
■
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Because the Config tab requires that a specific design is running in the FPGA at a
specific clock speed, writing a 0 to SRST; writing a 1, 2, or 3 to OCR2; or changing the
PSO value can cause the Board Test System to stop running.
JTAG Chain
This control shows all the devices currently in the JTAG chain. The Arria II GX device
is always the first device in the chain.
Uninstalling the shunt jumper from jumper J9 pins 1-2 includes the MAX II device in
the JTAG chain.
Board Information
This control displays static information about your board.
■
■
Flash Memory Map
This control shows the memory map of the flash memory device on your board.
PSR—Sets the MAX II PSR register. The numerical values in the list corresponds to
the page of flash memory to load during FPGA reconfiguration. Refer to
for more information.
PSS—Displays the MAX II PSS register value. Refer to
available options.
OCR1—Sets the MAX II OCR1 register. Refer to
options.
SRST—Resets the system and reloads the FPGA with a design from flash memory
based on the other MAX II register values. Refer to
MAX-II rev—Indicates the version of MAX II code currently running on the
board. The MAX II code resides in the <install
dir>\kits\arriaIIGX_2agx125_fpga\examples directory. Newer revisions of this
code might be available on the
Altera website.
MAC—Indicates the MAC address of the board.
Arria II GX FPGA Development Kit
Table 6–1
Table 6–1
Table 6–1
February 2011 Altera Corporation
for the list of available
Chapter 6: Board Test System
for more information.
Using the Board Test System
for the list of
page of the
Table 6–1