DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 29

• Manufacturer Part Number: DK-DEV-2AGX125N
• Description: KIT DEV ARRIA II GX FPGA 2AGX125
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX125N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX125EF35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2600

Chapter 6: Board Test System
Using the Board Test System
February 2011 Altera Corporation
1
1
Read
The Read control reads the flash memory on your board. To see the flash memory
contents, type a starting address in the text box and click Read. Values starting at the
specified address appear in the table. The base address of flash memory in this
Nios II-based BTS design is 0x0800.0000. The valid address range within the 64-MB
flash memory is 0x0000.0000 through 0x03FF.FFFF, as shown in the GUI.
If you enter an address outside of the 0x0000.0000 to 0x003F.FFFF flash memory
address space, a warning message identifies the valid flash memory address range.
Write
The Write control writes the flash memory on your board. To update the flash
memory contents, change values in the table and click Write. The application writes
the new values to flash memory and then reads the values back to guarantee that the
graphical display accurately reflects the memory contents.
To prevent overwriting the dedicated portions of flash memory, the application limits
the writable flash memory address range from 0x03FE.0000 to 0x003F.FFFF (which
corresponds to the unused flash memory address range shown in
page 6–2
Random Test
Starts a random data pattern test to flash memory. Limited to scratch page in the
upper 128K block.
CFI Query
The CFI Query control updates the memory table, displaying the CFI ROM table
contents from the flash device.
Increment Test
Starts an incrementing data pattern test to flash memory. Limited to scratch page in
the upper 128K block.
Reset
The Reset control executes the flash device’s reset command and updates the memory
table displayed on the Flash tab.
Erase
Erases flash memory. Limited to scratch page in the upper 128K blocks.
Flash Memory Map
Displays the flash memory map for the Arria II GX FPGA Development Kit.
and
Table A–1 on page
A–1).
Arria II GX FPGA Development Kit User Guide
Figure 6–1 on
6–9