C8051T630DK Silicon Laboratories Inc, C8051T630DK Datasheet - Page 97
![KIT DEV FOR C8051T630 FAMILY](/photos/9/23/92351/c8051t630dk_sml.jpg)
C8051T630DK
Manufacturer Part Number
C8051T630DK
Description
KIT DEV FOR C8051T630 FAMILY
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051T630DK
Contents
Board, daughter boards, power adapter, cables, documentation and software
Processor To Be Evaluated
C8051T63x
Interface Type
USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051T630, T631, T632, T633, T634 and T635 MCUs
For Use With
336-1465 - BOARD SOCKET DAUGHTER 20-QFN
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1464
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18.2. Power-Fail Reset/V
When a power-down transition or power irregularity causes V
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 18.2). When V
to a level above V
memory contents are not altered by the power-fail reset, it is impossible to determine if V
the level required for data retention. If the PORSF flag reads 1, the data may no longer be valid. The V
monitor is enabled after power-on resets. Its defined state (enabled/disabled) is not altered by any other
reset source. For example, if the V
V
Important Note: If the V
is selected as a reset source. Selecting the V
lized may cause a system reset. In some applications, this reset may be undesirable. If this is not desirable
in the application, a delay should be introduced between enabling the monitor and selecting it as a reset
source. The procedure for enabling the V
state is shown below:
1. Enable the V
2. If necessary, wait for the V
3. Select the V
See Figure 18.2 for V
monitor reset. See Table 5.4 for complete electrical characteristics of the V
DD
monitor will still be disabled after the reset.
DD
DD
RST
monitor as a reset source (PORSF bit in RSTSRC = 1).
monitor (VDMEN bit in VDM0CN = 1).
, the CIP-51 will be released from the reset state. Note that even though internal data
DD
DD
monitor timing; note that the power-on-reset delay is not incurred after a V
monitor is being turned on from a disabled state, it should be enabled before it
DD
DD
monitor to stabilize (see Table 5.4 for the V
DD
Monitor
monitor is disabled by code and a software reset is performed, the
DD
monitor and configuring it as a reset source from a disabled
DD
Rev. 1.0
monitor as a reset source before it is enabled and stabi-
C8051T630/1/2/3/4/5
DD
to drop below V
DD
DD
monitor.
Monitor turn-on time).
RST
, the power supply
DD
dropped below
DD
returns
DD
DD
97
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