C8051T630DK Silicon Laboratories Inc, C8051T630DK Datasheet - Page 125

• Manufacturer Part Number: C8051T630DK
• Description: KIT DEV FOR C8051T630 FAMILY
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051T630DK

• Contents: Board, daughter boards, power adapter, cables, documentation and software
• Processor To Be Evaluated: C8051T63x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051T630, T631, T632, T633, T634 and T635 MCUs
• For Use With: 336-1465 - BOARD SOCKET DAUGHTER 20-QFN
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1464

SFR Definition 20.14. P1SKIP: Port 1 Skip
SFR Address = 0xD5
SFR Definition 20.15. P2: Port 2
SFR Address = 0xA0; Bit-Addressable
Name
Reset
Name
Reset
Bit
6:0
Bit
7:1
Type
Type
7
0
Bit
Bit
Unused
P1SKIP[6:0]
Name
P2[0]
Unused
Name
R
R
7
0
7
0
Unused.
Port 2 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Unused. Read = 0b; Write = Don’t Care.
Port 1 Crossbar Skip Enable Bits.
These bits select Port 1 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
R
6
0
6
0
Description
R
5
0
5
0
Rev. 1.0
Don’t Care
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
R
4
0
4
0
P1SKIP[6:0]
Function
Write
R/W
R
3
0
3
0
C8051T630/1/2/3/4/5
R
2
0
2
0
000000b
0: P2.0 Port pin is logic
LOW.
1: P2.0 Port pin is logic
HIGH.
R
1
0
1
0
Read
P2[0]
R/W
0
0
0
1
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