C8051T630DK Silicon Laboratories Inc, C8051T630DK Datasheet - Page 13

KIT DEV FOR C8051T630 FAMILY

C8051T630DK

Manufacturer Part Number
C8051T630DK
Description
KIT DEV FOR C8051T630 FAMILY
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051T630DK

Contents
Board, daughter boards, power adapter, cables, documentation and software
Processor To Be Evaluated
C8051T63x
Interface Type
USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051T630, T631, T632, T633, T634 and T635 MCUs
For Use With
336-1465 - BOARD SOCKET DAUGHTER 20-QFN
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1464
C8051T630/1/2/3/4/5
SFR Definition 20.5. P1MASK: Port 1 Mask Register ................................................. 120
SFR Definition 20.6. P1MAT: Port 1 Match Register .................................................. 120
SFR Definition 20.7. P0: Port 0 ................................................................................... 121
SFR Definition 20.8. P0MDIN: Port 0 Input Mode ....................................................... 122
SFR Definition 20.9. P0MDOUT: Port 0 Output Mode ................................................ 122
SFR Definition 20.10. P0SKIP: Port 0 Skip ................................................................. 123
SFR Definition 20.11. P1: Port 1 ................................................................................. 123
SFR Definition 20.12. P1MDIN: Port 1 Input Mode ..................................................... 124
SFR Definition 20.13. P1MDOUT: Port 1 Output Mode .............................................. 124
SFR Definition 20.14. P1SKIP: Port 1 Skip ................................................................. 125
SFR Definition 20.15. P2: Port 2 ................................................................................. 125
SFR Definition 20.16. P2MDOUT: Port 2 Output Mode .............................................. 126
SFR Definition 21.1. SMB0CF: SMBus Clock/Configuration ...................................... 133
SFR Definition 21.2. SMB0CN: SMBus Control .......................................................... 135
SFR Definition 21.3. SMB0ADR: SMBus Slave Address ............................................ 137
SFR Definition 21.4. SMB0ADM: SMBus Slave Address Mask .................................. 138
SFR Definition 21.5. SMB0DAT: SMBus Data ............................................................ 139
SFR Definition 22.1. SCON0: Serial Port 0 Control .................................................... 153
SFR Definition 22.2. SBUF0: Serial (UART0) Port Data Buffer .................................. 154
SFR Definition 23.1. SPI0CFG: SPI0 Configuration ................................................... 163
SFR Definition 23.2. SPI0CN: SPI0 Control ............................................................... 164
SFR Definition 23.3. SPI0CKR: SPI0 Clock Rate ....................................................... 165
SFR Definition 23.4. SPI0DAT: SPI0 Data ................................................................. 165
SFR Definition 24.1. CKCON: Clock Control .............................................................. 170
SFR Definition 24.2. TCON: Timer Control ................................................................. 175
SFR Definition 24.3. TMOD: Timer Mode ................................................................... 176
SFR Definition 24.4. TL0: Timer 0 Low Byte ............................................................... 177
SFR Definition 24.5. TL1: Timer 1 Low Byte ............................................................... 177
SFR Definition 24.6. TH0: Timer 0 High Byte ............................................................. 178
SFR Definition 24.7. TH1: Timer 1 High Byte ............................................................. 178
SFR Definition 24.8. TMR2CN: Timer 2 Control ......................................................... 182
SFR Definition 24.9. TMR2RLL: Timer 2 Reload Register Low Byte .......................... 183
SFR Definition 24.10. TMR2RLH: Timer 2 Reload Register High Byte ...................... 183
SFR Definition 24.11. TMR2L: Timer 2 Low Byte ....................................................... 183
SFR Definition 24.12. TMR2H Timer 2 High Byte ....................................................... 184
SFR Definition 24.13. TMR3CN: Timer 3 Control ....................................................... 188
SFR Definition 24.14. TMR3RLL: Timer 3 Reload Register Low Byte ........................ 189
SFR Definition 24.15. TMR3RLH: Timer 3 Reload Register High Byte ...................... 189
SFR Definition 24.16. TMR3L: Timer 3 Low Byte ....................................................... 189
SFR Definition 24.17. TMR3H Timer 3 High Byte ....................................................... 190
SFR Definition 25.1. PCA0CN: PCA Control .............................................................. 204
SFR Definition 25.2. PCA0MD: PCA Mode ................................................................ 205
SFR Definition 25.3. PCA0PWM: PCA PWM Configuration ....................................... 206
SFR Definition 25.4. PCA0CPMn: PCA Capture/Compare Mode .............................. 207
SFR Definition 25.5. PCA0L: PCA Counter/Timer Low Byte ...................................... 208
Rev. 1.0
13

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