C8051T630DK Silicon Laboratories Inc, C8051T630DK Datasheet - Page 36

• Manufacturer Part Number: C8051T630DK
• Description: KIT DEV FOR C8051T630 FAMILY
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051T630DK

• Contents: Board, daughter boards, power adapter, cables, documentation and software
• Processor To Be Evaluated: C8051T63x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051T630, T631, T632, T633, T634 and T635 MCUs
• For Use With: 336-1465 - BOARD SOCKET DAUGHTER 20-QFN
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1464

C8051T630/1/2/3/4/5
6.3.3. Settling Time Requirements
A minimum tracking time is required before each conversion to ensure that an accurate conversion is per-
formed. This tracking time is determined by any series impedance, including the AMUX0 resistance, the
the ADC0 sampling capacitance, and the accuracy required for the conversion. Note that in delayed track-
ing mode, three SAR clocks are used for tracking at the start of every conversion. For many applications,
these three SAR clocks will meet the minimum tracking time requirements.
Figure 6.3 shows the equivalent ADC0 input circuit. The required ADC0 settling time for a given settling
accuracy (SA) may be approximated by Equation 6.1. See Table 5.9 for ADC0 minimum settling time
requirements as well as the mux impedance and sampling capacitor values.
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
R
n is the ADC resolution in bits (10).
36
TOTAL
is the sum of the AMUX0 resistance and any external source resistance.
Note: See electrical specification tables for R
Input Pin
Equation 6.1. ADC0 Settling Time Requirements
Figure 6.3. ADC0 Equivalent Input Circuits
t
=
RC
MUX Select
ln
Input


------ -
SA
= R
2
n


MUX

* C
Rev. 1.0
R
R
TOTAL
SAMPLE
MUX
C
SAMPLE
MUX
and C
C
SAMPLE
SAMPLE
parameters.