C8051T630DK Silicon Laboratories Inc, C8051T630DK Datasheet - Page 109
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C8051T630DK
Manufacturer Part Number
C8051T630DK
Description
KIT DEV FOR C8051T630 FAMILY
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051T630DK
Contents
Board, daughter boards, power adapter, cables, documentation and software
Processor To Be Evaluated
C8051T63x
Interface Type
USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051T630, T631, T632, T633, T634 and T635 MCUs
For Use With
336-1465 - BOARD SOCKET DAUGHTER 20-QFN
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1464
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20. Port Input/Output
Digital and analog resources are available through 17 I/O pins. Port pins P0.0-P1.7 can be defined as gen-
eral-purpose I/O (GPIO), assigned to one of the internal digital resources,Para1 or assigned to an analog
function as shown in Figure 20.3. Port pin P2.0 on can be used as GPIO and is shared with the C2 Inter-
face Data signal (C2D). The designer has complete control over which functions are assigned, limited only
by the number of physical I/O pins. This resource assignment flexibility is achieved through the use of a
Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in the corresponding
Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 20.3 and Figure 20.4). The registers XBR0 and XBR1, defined in SFR Definition 20.1 and SFR
Definition 20.2, are used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 20.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1). Complete
Electrical Specifications for Port I/O are given in Table 5.3 on page 25.
Highest
Priority
Lowest
Priority
SYSCLK
Outputs
SMBus
T0, T1
UART
P0
P1
P2
PCA
CP0
SPI
(P0.0-P0.7)
(P1.0-P1.7)
Figure 20.1. Port I/O Functional Block Diagram
(P2.0)
2
4
2
2
4
2
8
8
1
PnSKIP Registers
Rev. 1.0
XBR0, XBR1,
Crossbar
Decoder
Priority
Digital
(ADC0, CP0, VREF, EXTCLK)
To Analog Peripherals
C8051T630/1/2/3/4/5
8
8
P0MASK, P0MAT
P1MASK, P1MAT
Port Match
Cells
Cells
Cell
P0
I/O
P1
I/O
P2
I/O
PnMDIN Registers
External Interrupts
EX0 and EX1
PnMDOUT,
P0.0
P0.7
P1.0
P1.7
P2.0
109
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