C8051T630DK Silicon Laboratories Inc, C8051T630DK Datasheet
C8051T630DK
Specifications of C8051T630DK
Related parts for C8051T630DK
C8051T630DK Summary of contents
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Analog Peripherals - 10-Bit ADC (‘T630/2/4 only 500 ksps • external inputs • VREF from on-chip VREF, external pin, • Internal Regulator Internal or external start of conversion source • Built-in temperature ...
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C8051T630/1/2/3/4/5 2 Rev. 1.0 ...
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Table of Contents 1. System Overview ..................................................................................................... 15 2. Ordering Information ............................................................................................... 17 3. Pin Definitions.......................................................................................................... 18 4. QFN-20 Package Specifications ............................................................................. 21 5. Electrical Characteristics ........................................................................................ 23 5.1. Absolute Maximum Specifications..................................................................... 23 5.2. Electrical Characteristics ................................................................................... 24 5.3. Typical ...
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C8051T630/1/2/3/4/5 15. Interrupts ................................................................................................................ 80 15.1. MCU Interrupt Sources and Vectors................................................................ 81 15.1.1. Interrupt Priorities.................................................................................... 81 15.1.2. Interrupt Latency ..................................................................................... 81 15.2. Interrupt Register Descriptions ........................................................................ 82 15.3. INT0 and INT1 External Interrupts................................................................... 87 16. EPROM Memory ..................................................................................................... 89 16.1. ...
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Priority Crossbar Decoder ............................................................................. 114 20.4. Port I/O Initialization ...................................................................................... 116 20.5. Port Match ..................................................................................................... 118 20.6. Special Function Registers for Accessing and Configuring Port I/O ............. 121 21. SMBus................................................................................................................... 127 21.1. Supporting Documents .................................................................................. 128 21.2. SMBus Configuration..................................................................................... ...
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C8051T630/1/2/3/4/5 24.1.1. Mode 0: 13-bit Counter/Timer ............................................................... 171 24.1.2. Mode 1: 16-bit Counter/Timer ............................................................... 172 24.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload..................................... 173 24.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................ 174 24.2. Timer 2 .......................................................................................................... 179 24.2.1. 16-bit ...
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List of Figures 1. System Overview Figure 1.1. C8051T630/1/2/3/4/5 Block Diagram .................................................... 16 3. Pin Definitions Figure 3.1. QFN-20 Pinout Diagram (Top View) ..................................................... 20 4. QFN-20 Package Specifications Figure 4.1. QFN-20 Package Drawing .................................................................... 21 Figure 4.2. QFN-20 Recommended ...
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C8051T630/1/2/3/4/5 Figure 20.4. Crossbar Priority Decoder with Crystal Pins Skipped ....................... 115 21. SMBus Figure 21.1. SMBus Block Diagram ...................................................................... 127 Figure 21.2. Typical SMBus Configuration ............................................................ 128 Figure 21.3. SMBus Transaction ........................................................................... 129 Figure 21.4. Typical SMBus SCL Generation ...
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Figure 25.4. PCA Capture Mode Diagram ............................................................. 195 Figure 25.5. PCA Software Timer Mode Diagram ................................................. 196 Figure 25.6. PCA High-Speed Output Mode Diagram ........................................... 197 Figure 25.7. PCA Frequency Output Mode ........................................................... 198 Figure 25.8. PCA 8-Bit PWM Mode ...
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C8051T630/1/2/3/4/5 List of Tables 2. Ordering Information Table 2.1. Product Selection Guide ......................................................................... 17 3. Pin Definitions Table 3.1. Pin Definitions for the C8051T630/1/2/3/4/5 ........................................... 18 4. QFN-20 Package Specifications Table 4.1. QFN-20 Package Dimensions ................................................................ 21 Table 4.2. QFN-20 ...
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UART0 Table 22.1. Timer Settings for Standard Baud Rates Using The Internal 24.5 MHz Oscillator .............................................. 155 Table 22.2. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz Oscillator ......................................... 155 23. Enhanced Serial Peripheral ...
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C8051T630/1/2/3/4/5 List of Registers SFR Definition 6.1. ADC0CF: ADC0 Configuration ...................................................... 37 SFR Definition 6.2. ADC0H: ADC0 Data Word MSB .................................................... 38 SFR Definition 6.3. ADC0L: ADC0 Data Word LSB ...................................................... 38 SFR Definition 6.4. ADC0CN: ADC0 Control ................................................................ 39 ...
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SFR Definition 20.5. P1MASK: Port 1 Mask Register ................................................. 120 SFR Definition 20.6. P1MAT: Port 1 Match Register .................................................. 120 SFR Definition 20.7. P0: Port 0 ................................................................................... 121 SFR Definition 20.8. P0MDIN: Port 0 Input Mode ....................................................... 122 SFR Definition ...
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C8051T630/1/2/3/4/5 SFR Definition 25.6. PCA0H: PCA Counter/Timer High Byte ..................................... 208 SFR Definition 25.7. PCA0CPLn: PCA Capture Module Low Byte ............................. 209 SFR Definition 25.8. PCA0CPHn: PCA Capture Module High Byte ........................... 209 C2 Register Definition 26.1. C2ADD: C2 Address ...
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System Overview C8051T630/1/2/3/4/5 devices are fully integrated, mixed-signal, system-on-a-chip MCUs. Highlighted fea- tures are listed below. Refer to Table 2.1 for specific product feature selection and part ordering numbers. High-speed pipelined 8051-compatible microcontroller core ( MIPS) ...
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C8051T630/1/2/3/4/5 Power On CIP-51 8051 Reset Controller Core Reset 8/4/2k Byte EPROM Program Memory Debug / C2CK/RST Programming Hardware 256 Byte SRAM C2D 512 Byte XRAM Peripheral Power VDD Regulator Core Power GND Precision 24.5 MHz Oscillator Low-Freq. Oscillator External ...
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Ordering Information Table 2.1. Product Selection Guide C8051T630-GM 25 8k* 768 Y C8051T631-GM 25 8k* 768 Y C8051T632- 768 Y C8051T633- 768 Y C8051T634- 768 Y C8051T635- 768 Y * 512 ...
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C8051T630/1/2/3/4/5 3. Pin Definitions Table 3.1. Pin Definitions for the C8051T630/1/2/3/4/5 Name Pin Type Description V 3 Power Supply Voltage. DD GND 2 Ground. RST I/O Device Reset. Open-drain output of internal POR or V external source can ...
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Table 3.1. Pin Definitions for the C8051T630/1/2/3/4/5 (Continued) Name Pin Type Description P0 I/O or Port 0. P1 I/O or Port 1. P1 I/O or Port 1. P1.2 ...
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C8051T630/1/2/3/4/5 P0.0 1 GND 2 VDD 3 RST/C2CK 4 P2.0/C2D 5 Figure 3.1. QFN-20 Pinout Diagram (Top View) 20 C8051T630/1/2/3/4/5 Top View GND Rev. 1.0 P0.6/ 15 CNVSTR 14 P0.7 13 P1.0 12 P1.1 11 P1.2 ...
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QFN-20 Package Specifications Figure 4.1. QFN-20 Package Drawing Table 4.1. QFN-20 Package Dimensions Dimension Min Typ A 0.80 0.90 A1 0.00 0.02 b 0.18 0.25 D 4.00 BSC. D2 2.00 2.15 e 0.50 BSC. E 4.00 BSC. E2 2.00 ...
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C8051T630/1/2/3/4/5 Figure 4.2. QFN-20 Recommended PCB Land Pattern Table 4.2. QFN-20 PCB Land Pattern Dimesions Dimension Min C1 3.70 C2 3.70 E 0.50 X1 0.20 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning ...
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Electrical Characteristics 5.1. Absolute Maximum Specifications Table 5.1. Absolute Maximum Ratings Parameter Ambient temperature under bias Storage Temperature Voltage on RST or any Port I/O Pin (except V during programming) with PP respect to GND Voltage on V with ...
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C8051T630/1/2/3/4/5 5.2. Electrical Characteristics Table 5.2. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Supply Voltage (Note 1) Regulator in Normal Mode Regulator in Bypass Mode Digital Supply Current with V DD CPU ...
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Table 5.3. Port I/O DC Electrical Characteristics V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameters Output High Voltage I = –3 mA, Port I/O push-pull –10 µA, Port I/O push-pull ...
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C8051T630/1/2/3/4/5 Table 5.4. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter RST Output Low Voltage RST Input High Voltage RST Input Low Voltage RST Input Pullup Current RST = 0 POR ...
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Table 5.7. Internal High-Frequency Oscillator Electrical Characteristics V = 1 –40 to +85 °C unless otherwise specified. Use factory-calibrated settings Parameter Oscillator Frequency IFCN = 11b Oscillator Supply Current 25 °C, V ...
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C8051T630/1/2/3/4/5 Table 5.9. ADC0 Electrical Characteristics V = 3.0 V, VREF = 2.40 V (REFSL=0), DD Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Offset Temperature Coefficient Dynamic performance (10 kHz sine-wave single-ended input, 1 ...
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Table 5.10. Temperature Sensor Electrical Characteristics V – +85 °C unless otherwise specified. DD Parameter Linearity Slope Slope Error* Offset Temp = 0 °C Offset Error* Temp = 0 °C Note: Represents one standard deviation ...
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C8051T630/1/2/3/4/5 Table 5.12. IDAC Electrical Characteristics V – +85 °C Full-scale output current set unless otherwise specified. DD Parameter Static Performance Resolution Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Output Compliance Range Offset ...
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Table 5.13. Comparator Electrical Characteristics V = 3.0 V, –40 to +85 °C unless otherwise noted. DD Parameter Response Time: CP0+ – CP0– = 100 mV * Mode 0, Vcm = 1.5 V CP0+ – CP0– = –100 mV Response ...
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C8051T630/1/2/3/4/5 5.3. Typical Performance Curves 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 Figure 5.1. Normal Mode Digital Supply Current vs. Frequency (MPCE = 1) 2.5 2.0 1.5 1.0 0.5 0 Figure 5.2. Idle Mode ...
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ADC (ADC0, C8051T630/2/4 only) ADC0 on the C8051T630/2 500 ksps, 10-bit successive-approximation-register (SAR) ADC with integrated track-and-hold, a gain stage programmable 0.5x, and a programmable window detector. The ADC is fully configurable under ...
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C8051T630/1/2/3/4/5 6.1. Output Code Formatting The ADC measures the input voltage with reference to GND. The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion of each conversion. ...
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Tracking Modes The AD0TM bit in register ADC0CN enables "delayed conversions", and will delay the actual conversion start by three SAR clock cycles, during which time the ADC will continue to track the input. If AD0TM is left at ...
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C8051T630/1/2/3/4/5 6.3.3. Settling Time Requirements A minimum tracking time is required before each conversion to ensure that an accurate conversion is per- formed. This tracking time is determined by any series impedance, including the AMUX0 resistance, the the ADC0 sampling ...
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SFR Definition 6.1. ADC0CF: ADC0 Configuration Bit 7 6 AD0SC[4:0] Name Type 1 1 Reset SFR Address = 0xBC Bit Name 7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following ...
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C8051T630/1/2/3/4/5 SFR Definition 6.2. ADC0H: ADC0 Data Word MSB Bit 7 6 Name Type 0 0 Reset SFR Address = 0xBE Bit Name 7:0 ADC0H[7:0] ADC0 Data Word High-Order Bits. For AD0LJST = 0: Bits 7–2 will read 000000b. Bits ...
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SFR Definition 6.4. ADC0CN: ADC0 Control Bit 7 6 AD0EN AD0TM AD0INT Name R/W R/W Type 0 0 Reset SFR Address = 0xE8; Bit-Addressable Bit Name 7 AD0EN ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ...
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C8051T630/1/2/3/4/5 6.4. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro- grammed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code ...
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SFR Definition 6.7. ADC0LTH: ADC0 Less-Than Data High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0xC6 Bit Name 7:0 ADC0LTH[7:0] ADC0 Less-Than Data Word High-Order Bits. SFR Definition 6.8. ADC0LTL: ADC0 Less-Than Data Low Byte ...
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C8051T630/1/2/3/4/5 6.4.1. Window Detector Example Figure 6.4 shows two example ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). The input voltage can range from 0 to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit ...
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ADC0 Analog Multiplexer (C8051T630/2/4 only) ADC0 on the C8051T630/2/4 uses an analog input multiplexer to select the positive input to the ADC. Any of the following may be selected as the positive input: Port 0 and 1 I/O pins, ...
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C8051T630/1/2/3/4/5 SFR Definition 6.9. AMX0P: AMUX0 Positive Channel Select Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xBB Bit Name 7:5 Unused Unused. Read = 000b; Write = Don’t Care. 4:0 AMX0P[4:0] AMUX0 Positive Input ...
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Temperature Sensor (C8051T630/2/4 only) An on-chip temperature sensor is included on the C8051T630/2/4 which can be directly accessed via the ADC multiplexer. To use the ADC to measure the temperature sensor, the ADC mux channel should be configured to ...
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C8051T630/1/2/3/4/5 5.00 4.00 3.00 2.00 1.00 0.00 -40.00 -20.00 -1.00 -2.00 -3.00 -4.00 -5.00 Figure 7.2. Temperature Sensor Error with 1-Point Calibration at 0 Celsius 46 0.00 20.00 40.00 Temperature (degrees C) Rev. 1.0 5.00 4.00 3.00 2.00 1.00 0.00 ...
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SFR Definition 7.1. TOFFH: Temperature Offset Measurement High Byte Bit 7 6 Name Type Varies Varies Varies Reset SFR Address = 0x86 Bit Name 7:0 TOFF[9:2] Temperature Sensor Offset High Order Bits. The temperature sensor offset registers represent the output ...
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C8051T630/1/2/3/4/5 8. 10-Bit Current Mode DAC (IDA0, C8051T630/2/4 only) The C8051T630/2/4 device includes a 10-bit current-mode Digital-to-Analog Converter (IDAC). The maxi- mum current output of the IDAC can be adjusted for three different current settings; 0.5 mA, 1 mA, and ...
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Update Output Based on Timer Overflow Similar to the ADC operation, in which an ADC conversion can be initiated by a timer overflow indepen- dently of the processor, the IDAC outputs can use a Timer overflow to schedule an ...
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C8051T630/1/2/3/4/5 SFR Definition 8.1. IDA0CN: IDA0 Control Bit 7 6 IDA0EN IDA0CM[2:0] Name R/W Type 0 1 Reset SFR Address = 0xB9 Bit Name 7 IDA0EN IDA0 Enable. 0: IDA0 Disabled. 1: IDA0 Enabled. 6:4 IDA0CM[2:0] IDA0 Update Source Select ...
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SFR Definition 8.2. IDA0H: IDA0 Data Word MSB Bit 7 6 Name Type 0 0 Reset SFR Address = 0x97 Bit Name 7:0 IDA0[9:2] IDA0 Data Word High-Order Bits. Upper 8 bits of the 10-bit IDA0 Data Word. SFR Definition ...
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C8051T630/1/2/3/4/5 9. Voltage Reference Options The Voltage reference multiplexer for the ADC is configurable to use an externally connected voltage refer- ence, the on-chip reference voltage generator routed to the VREF pin, the unregulated power supply volt- age (V ), ...
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REF0CN VDD External Voltage Reference R1 Circuit VREF GND 0 + 4.7F 0.1F VDD 1 Recommended Bypass Capacitors Figure 9.1. Voltage Reference Functional Block Diagram Rev. 1.0 C8051T630/1/2/3/4/5 To ADC, IDAC, EN Internal Oscillators, Bias Generator Reference, TempSensor IOSCEN EN ...
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C8051T630/1/2/3/4/5 SFR Definition 9.1. REF0CN: Reference Control Bit 7 6 REFBGS Name R/W R Type 0 0 Reset SFR Address = 0xD1 Bit Name 7 REFBGS Reference Buffer Gain Select. This bit selects between 1x and 2x gain for the ...
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Voltage Regulator (REG0) C8051T630/1/2/3/4/5 devices include an internal voltage regulator (REG0) to regulate the internal core supply to 1.8 V from a V supply of 1.8 to 3.6 V. Two power-saving modes are built into the regulator to DD ...
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C8051T630/1/2/3/4/5 SFR Definition 10.1. REG0CN: Voltage Regulator Control Bit 7 6 STOPCF BYPASS Name R/W R/W Type 0 0 Reset SFR Address = 0xC7 Bit Name 7 STOPCF Stop Mode Configuration. This bit configures the regulator’s behavior when the device ...
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Comparator0 C8051T630/1/2/3/4/5 devices include an on-chip programmable voltage comparator, Comparator0, shown in Figure 11.1. The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous ...
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C8051T630/1/2/3/4/5 The Comparator response time may be configured in software via the CPT0MD register (see SFR Defini- tion 11.2). Selecting a longer response time reduces the Comparator supply current. CP0+ VIN+ + CP0 CP0- _ VIN- CIRCUIT CONFIGURATION Positive Hysteresis ...
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SFR Definition 11.1. CPT0CN: Comparator0 Control Bit 7 6 CP0EN CP0OUT CP0RIF Name R/W R Type 0 0 Reset SFR Address = 0x9B Bit Name 7 CP0EN Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. 6 CP0OUT Comparator0 Output ...
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C8051T630/1/2/3/4/5 SFR Definition 11.2. CPT0MD: Comparator0 Mode Selection Bit 7 6 CP0RIE Name R R Type 0 0 Reset SFR Address = 0x9D Bit Name 7:6 Unused Unused. Read = 00b, Write = Don’t Care. 5 CP0RIE Comparator0 Rising-Edge Interrupt ...
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Comparator Multiplexer C8051T630/1/2/3/4/5 devices include an analog input multiplexer to connect Port I/O pins to the compara- tor inputs. The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 11.3). The CMX0P3–CMX0P0 bits select the Comparator0 positive input; ...
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C8051T630/1/2/3/4/5 SFR Definition 11.3. CPT0MX: Comparator0 MUX Selection Bit 7 6 CMX0N[3:0] Name R/W Type 1 1 Reset SFR Address = 0x9F Bit Name 7:4 CMX0N[3:0] Comparator0 Negative Input MUX Selection. 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1xxx: ...
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CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a superset ...
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C8051T630/1/2/3/4/5 With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execu- tion ...
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Table 12.1. CIP-51 Instruction Set Summary Mnemonic Description Arithmetic Operations ADD A, Rn Add register to A ADD A, direct Add direct byte to A ADD A, @Ri Add indirect RAM to A ADD A, #data Add immediate to A ...
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C8051T630/1/2/3/4/5 Table 12.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description XRL direct, #data Exclusive-OR immediate to direct byte CLR A Clear A CPL A Complement Rotate A left RLC A Rotate A left through Carry RR A ...
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Table 12.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description ANL C, bit AND direct bit to Carry ANL C, /bit AND complement of direct bit to Carry ORL C, bit OR direct bit to carry ORL C, /bit OR complement ...
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C8051T630/1/2/3/4/5 Notes on Registers, Operands and Addressing Modes Register R0–R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (twos complement) offset relative to the first ...
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CIP-51 Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should always be written to the value indicated in the SFR description. Future product versions may use these bits to ...
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C8051T630/1/2/3/4/5 SFR Definition 12.3. SP: Stack Pointer Bit 7 6 Name Type 0 0 Reset SFR Address = 0x81 Bit Name 7:0 SP[7:0] Stack Pointer. The Stack Pointer holds the location of the top of the stack. The stack pointer ...
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SFR Definition 12.6. PSW: Program Status Word Bit Name R/W R/W Type 0 0 Reset SFR Address = 0xD0; Bit-Addressable Bit Name 7 CY Carry Flag. This bit is set when the last arithmetic operation resulted ...
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C8051T630/1/2/3/4/5 13. Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space ...
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Program Memory The CIP-51 core has program memory space. The C8051T630/1 implements 8192 bytes of this program memory space as in-system, Byte-Programmable EPROM, organized in a contiguous block from addresses 0x0000 to 0x1FFF. Note that 512 ...
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C8051T630/1/2/3/4/5 13.2.1.1. General Purpose Registers The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of gen- eral-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only one of ...
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SFR Definition 13.1. EMI0CN: External Memory Interface Control Bit 7 6 Name R/W R/W Type 0 0 Reset SFR Address = 0xAA Bit Name 7:1 Unused Unused. Read = 0000000b; Write = Don’t Care 0 PGSEL XRAM Page Select. The ...
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C8051T630/1/2/3/4/5 14. Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the C8051T630/1/2/3/4/5's resources and peripherals. The CIP-51 controller core duplicates the SFRs ...
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Table 14.2. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address 0xE0 Accumulator ACC 0xBC ADC0 Configuration ADC0CF 0xE8 ADC0 Control ADC0CN 0xC4 ADC0 Greater-Than Compare High ADC0GTH 0xC3 ADC0 Greater-Than Compare ...
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C8051T630/1/2/3/4/5 Table 14.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address 0xFD Port 0 Match Configuration P0MAT 0xF1 Port 0 Input Mode Configuration P0MDIN 0xA4 Port 0 Output Mode Configuration ...
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Table 14.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address 0xD7 SMBus Slave Address SMB0ADR 0xC1 SMBus Configuration SMB0CF 0xC0 SMBus Control SMB0CN 0xC2 SMBus Data SMB0DAT 0x81 Stack Pointer ...
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C8051T630/1/2/3/4/5 15. Interrupts The C8051T630/1/2/3/4/5 includes an extended interrupt system supporting a total of 14 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external input pins varies according to the specific version of ...
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MCU Interrupt Sources and Vectors The C8051T630/1/2/3/4/5 MCUs support 14 interrupt sources. Software can simulate an interrupt by set- ting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated ...
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C8051T630/1/2/3/4/5 Table 15.1. Interrupt Summary Interrupt Source Interrupt Vector Reset 0x0000 External Interrupt 0 0x0003 (INT0) Timer 0 Overflow 0x000B External Interrupt 1 0x0013 (INT1) Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SPI0 0x0033 SMB0 0x003B Port ...
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SFR Definition 15.1. IE: Interrupt Enable Bit ESPI0 Name R/W R/W Type 0 0 Reset SFR Address = 0xA8; Bit-Addressable Bit Name 7 EA Enable All Interrupts. Globally enables/disables all interrupts. It overrides individual interrupt mask settings. ...
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C8051T630/1/2/3/4/5 SFR Definition 15.2. IP: Interrupt Priority Bit 7 6 PSPI0 Name R R/W Type 1 0 Reset SFR Address = 0xB8; Bit-Addressable Bit Name 7 Unused Unused. Read = 1, Write = Don't Care. 6 PSPI0 Serial Peripheral Interface ...
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SFR Definition 15.3. EIE1: Extended Interrupt Enable 1 Bit 7 6 ET3 Reserved Name R/W R/W Type 0 0 Reset SFR Address = 0xE6 Bit Name 7 ET3 Enable Timer 3 Interrupt. This bit sets the masking of the Timer ...
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C8051T630/1/2/3/4/5 SFR Definition 15.4. EIP1: Extended Interrupt Priority 1 Bit 7 6 PT3 Reserved Name R/W R/W Type 0 0 Reset SFR Address = 0xF6 Bit Name 7 PT3 Timer 3 Interrupt Priority Control. This bit sets the priority of ...
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INT0 and INT1 External Interrupts The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select active ...
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C8051T630/1/2/3/4/5 SFR Definition 15.5. IT01CF: INT0/INT1 Configuration Bit 7 6 IN1PL IN1SL[2:0] Name R/W Type 0 0 Reset SFR Address = 0xE4 Bit Name 7 IN1PL INT1 Polarity. 0: /INT1 input is active low. 1: /INT1 input is active high. ...
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EPROM Memory Electrically programmable read-only memory (EPROM) is included on-chip for program code storage. The EPROM memory can be programmed via the C2 debug and programming interface when a special pro- gramming voltage is applied to the V (i.e., ...
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C8051T630/1/2/3/4/5 16.1.2. EPROM Read Procedure 1. Reset the device using the /RST pin. 2. Wait at least 20 µs before sending the first C2 command. 3. Place the device in core reset: Write 0x04 to the DEVCTL register. 4. Write ...
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Program Memory CRC A CRC engine is included on-chip which provides a means of verifying EPROM contents once the device has been programmed. The CRC engine is available for EPROM verification even if the device is fully read and ...
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C8051T630/1/2/3/4/5 17. Power Management Modes The C8051T630/1/2/3/4/5 devices have three software programmable power management modes: idle, stop, and suspend. Idle mode and stop mode are part of the standard 8051 architecture, while suspend mode is an enhanced power-saving mode implemented ...
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WDT was initially configured to allow this operation. This pro- vides the opportunity for additional power savings, allowing the system to remain in the idle mode indefi- nitely, waiting for an ...
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C8051T630/1/2/3/4/5 SFR Definition 17.1. PCON: Power Control Bit 7 6 Name Type 0 0 Reset SFR Address = 0x87 Bit Name 7:2 GF[5:0] General Purpose Flags 5–0. These are general purpose flags for use under software control. 1 STOP Stop ...
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Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: CIP-51 halts program execution Special Function Registers (SFRs) are initialized to their ...
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C8051T630/1/2/3/4/5 18.1. Power-On Reset During power-up, the device is held in a reset state and the RST pin is driven low until delay occurs before the device is released from reset; the delay decreases as the ...
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Power-Fail Reset/V DD When a power-down transition or power irregularity causes V monitor will drive the RST pin low and hold the CIP- reset state (see Figure 18.2). When level above V , the ...
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C8051T630/1/2/3/4/5 SFR Definition 18.1. VDM0CN: V Bit 7 6 VDMEN VDDSTAT Name R/W R Type Varies Varies Reset SFR Address = 0xFF Bit Name 7 VDMEN V Monitor Enable. DD This bit turns the V tem resets until it is ...
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Comparator0 Reset Comparator0 can be configured as a reset source by writing the C0RSEF flag (RSTSRC.5). Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter on the ...
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C8051T630/1/2/3/4/5 SFR Definition 18.2. RSTSRC: Reset Source Bit 7 6 MEMERR C0RSEF Name R R Type 0 Varies Reset SFR Address = 0xEF Bit Name Description 7 Unused Unused. 6 MEMERR EPROM Error Reset Flag. 5 C0RSEF Comparator0 Reset Enable ...
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Oscillators and Clock Selection C8051T630/1/2/3/4/5 devices include a programmable internal high-frequency oscillator, a programmable internal low-frequency oscillator, and an external oscillator drive circuit. The internal high-frequency oscilla- tor can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, ...
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C8051T630/1/2/3/4/5 SFR Definition 19.1. CLKSEL: Clock Select Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xA9 Bit Name 7:2 Unused Unused. Read = 000000b; Write = Don’t Care 1:0 CLKSL[1:0] System Clock Source Select Bits. ...
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Programmable Internal High-Frequency (H-F) Oscillator All C8051T630/1/2/3/4/5 devices include a programmable internal high-frequency oscillator that defaults as the system clock after a system reset. The internal oscillator period caPara1n be adjusted via the OSCICL register as defined by SFR ...
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C8051T630/1/2/3/4/5 SFR Definition 19.3. OSCICN: Internal H-F Oscillator Control Bit 7 6 IOSCEN IFRDY SUSPEND Name R/W R Type 1 1 Reset SFR Address = 0xB2 Bit Name 7 IOSCEN Internal H-F Oscillator Enable Bit. 0: Internal H-F Oscillator Disabled. ...
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Programmable Internal Low-Frequency (L-F) Oscillator All C8051T630/1/2/3/4/5 devices include a programmable low-frequency internal oscillator, which is cali- brated to a nominal frequency of 80 kHz. The low-frequency oscillator circuit includes a divider that can be changed to divide the ...
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C8051T630/1/2/3/4/5 19.4. External Oscillator Drive Circuit The external oscillator circuit may drive an external capacitor or RC network. A CMOS clock may also pro- vide a clock input. In RC, capacitor, or CMOS clock configuration, the clock source should be ...
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SFR Definition 19.5. OSCXCN: External Oscillator Control Bit 7 6 XOSCMD[2:0] Name R Type 0 0 Reset SFR Address = 0xB1 Bit Name 7 Unused Read = 0; Write = Don’t Care 6:4 XOSCMD[2:0] External Oscillator Mode Select. 00x: External ...
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C8051T630/1/2/3/4/5 19.4.1. External RC Example network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 19.1, “RC Mode”. The capacitor should be no greater than 100 pF; ...
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Port Input/Output Digital and analog resources are available through 17 I/O pins. Port pins P0.0-P1.7 can be defined as gen- eral-purpose I/O (GPIO), assigned to one of the internal digital resources,Para1 or assigned to an analog function as shown ...
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C8051T630/1/2/3/4/5 20.1. Port I/O Modes of Operation Port pins use the Port I/O cell shown in Figure 20.2. Each Port I/O cell can be configured by software for analog I/O or digital I/O using the PnMDIN registers. On reset, all ...
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WEAKPUD (Weak Pull-Up Disable) PxMDOUT.x (1 for push-pull) (0 for open-drain) XBARE (Crossbar Enable) Px.x – Output Logic Value (Port Latch or Crossbar) PxMDIN.x (1 for digital) (0 for analog) To/From Analog Peripheral Px.x – Input Logic Value (Reads 0 ...
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C8051T630/1/2/3/4/5 20.2. Assigning Port I/O Pins to Analog and Digital Functions Port I/O pins can be assigned to various analog, digital, and external interrupt functions. The Port pins assigned to analog functions should be configured for analog I/O, and Port ...
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Assigning Port I/O Pins to External Digital Event Capture Functions External digital event capture functions can be used to trigger an interrupt or wake the device from a low power mode when a transition occurs on a digital I/O ...
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C8051T630/1/2/3/4/5 20.3. Priority Crossbar Decoder The Priority Crossbar Decoder (Figure 20.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource ...
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SF Signals VREF IDA EXTCLK PIN I TX0 RX0 SCK MISO MOSI NSS* SDA SCL CP0 CP0A SYSCLK CEX0 CEX1 CEX2 ECI P0SKIP[0:7] Port pin potentially available to peripheral SF ...
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C8051T630/1/2/3/4/5 20.4. Port I/O Initialization Port I/O initialization consists of the following steps: 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN). 2. Select the output mode (open-drain or push-pull) ...
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SFR Definition 20.1. XBR0: Port I/O Crossbar Register 0 Bit 7 6 CP0AE Name R R Type 0 0 Reset SFR Address = 0xE1 Bit Name 7:6 Unused Unused. Read = 00b; Write = Don’t Care. 5 CP0AE Comparator0 Asynchronous ...
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C8051T630/1/2/3/4/5 SFR Definition 20.2. XBR1: Port I/O Crossbar Register 1 Bit 7 6 Name WEAKPUD XBARE R/W R/W Type 0 0 Reset SFR Address = 0xE2 Bit Name 7 WEAKPUD Port I/O Weak Pullup Disable. 0: Weak Pullups enabled (except ...
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A Port mismatch event may be used to generate an interrupt or wake the device from a low power mode, such as IDLE or SUSPEND. See the Interrupts and Power Options chapters for more details on interrupt and wake-up sources. ...
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C8051T630/1/2/3/4/5 SFR Definition 20.5. P1MASK: Port 1 Mask Register Bit 7 6 Name Type 0 0 Reset SFR Address = 0xEE Bit Name 7:0 P1MASK[7:0] Port 1 Mask Value. Selects P1 pins to be compared to the corresponding bits in ...
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Special Function Registers for Accessing and Configuring Port I/O All Port I/O are accessed through corresponding special function registers (SFRs) that are both byte addressable and bit addressable. When writing to a Port, the value written to the SFR ...
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C8051T630/1/2/3/4/5 SFR Definition 20.8. P0MDIN: Port 0 Input Mode Bit 7 6 Name Type 1 1 Reset SFR Address = 0xF1 Bit Name 7:0 P0MDIN[7:0] Analog Configuration Bits for P0.7–P0.0 (respectively). Port pins configured for analog mode have their weak ...
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SFR Definition 20.10. P0SKIP: Port 0 Skip Bit 7 6 Name Type 0 0 Reset SFR Address = 0xD4 Bit Name 7:0 P0SKIP[7:0] Port 0 Crossbar Skip Enable Bits. These bits select Port 0 pins to be skipped by the ...
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C8051T630/1/2/3/4/5 SFR Definition 20.12. P1MDIN: Port 1 Input Mode Bit 7 6 Name Type 1 1 Reset SFR Address = 0xF2 Bit Name 7:0 P1MDIN[7:0] Analog Configuration Bits for P1.7–P1.0 (respectively). Port pins configured for analog mode have their weak ...
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SFR Definition 20.14. P1SKIP: Port 1 Skip Bit 7 6 Name R Type 0 0 Reset SFR Address = 0xD5 Bit Name 7 Unused Unused. Read = 0b; Write = Don’t Care. 6:0 P1SKIP[6:0] Port 1 Crossbar Skip Enable Bits. ...
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C8051T630/1/2/3/4/5 SFR Definition 20.16. P2MDOUT: Port 2 Output Mode Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xA6 Bit Name 7:1 Unused Unused. Read = 000000b; Write = Don’t Care 0 P2MDOUT[0] Output Configuration Bits ...
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SMBus The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I the interface by the system controller are byte oriented with the ...
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C8051T630/1/2/3/4/5 21.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents The I C-Bus and How to Use It (including specifications), Philips Semiconductor The I C-Bus Specification—Version ...
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All transactions are initiated by a master, with one or more addressed slave devices as the target. The master generates the START condition and then transmits the slave address and direction bit. If the trans- action is a WRITE operation ...
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C8051T630/1/2/3/4/5 When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeouts. Timer 3 is forced to reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled ...
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Table 21.1. SMBus Clock Source Selection SMBCS1 The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or when the Free Timeout detection is enabled. When operating as a ...
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C8051T630/1/2/3/4/5 after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 21.2 shows the min- imum setup and hold times ...
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SFR Definition 21.1. SMB0CF: SMBus Clock/Configuration Bit 7 6 ENSMB INH BUSY Name R/W R/W Type 0 0 Reset SFR Address = 0xC1 Bit Name 7 ENSMB SMBus Enable. This bit enables the SMBus interface when set to 1. When ...
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C8051T630/1/2/3/4/5 21.4.2. SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see SFR Definition 21.2). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used ...
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SFR Definition 21.2. SMB0CN: SMBus Control Bit 7 6 MASTER TXMODE Name R R Type 0 0 Reset SFR Address = 0xC0; Bit-Addressable Bit Name Description 7 MASTER SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating ...
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C8051T630/1/2/3/4/5 Table 21.3. Sources for Hardware Changes to SMB0CN Bit Set by Hardware When: A START is generated. MASTER START is generated. SMB0DAT is written before the start of an TXMODE SMBus frame. A START followed ...
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In this case, either value are acceptable on the incoming slave address. Additionally, if the GC bit ...
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C8051T630/1/2/3/4/5 SFR Definition 21.4. SMB0ADM: SMBus Slave Address Mask Bit 7 6 Name Type 1 1 Reset SFR Address = 0xE7 Bit Name 7:1 SLVM[6:0] SMBus Slave Address Mask. Defines which bits of register SMB0ADR are compared with an incoming ...
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Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is set. ...
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C8051T630/1/2/3/4/5 21.5. SMBus Transfer Modes The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave ...
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Read Sequence (Master) During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will be a transmitter during the address byte, and a receiver during all data bytes. The SMBus interface ...
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C8051T630/1/2/3/4/5 21.5.3. Write Sequence (Slave) During a write sequence, an SMBus master writes data to a slave device. The slave in this transfer will be a receiver during the address byte, and a receiver during all data bytes. When slave ...
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Read Sequence (Slave) During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will be a receiver during the address byte, and a transmitter during all data bytes. When slave events ...
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C8051T630/1/2/3/4/5 Table 21.5. SMBus Status Decoding With Hardware ACK Generation Disabled Values Read Current SMbus State A master START was gener- 1110 ated. A master data or address byte was transmitted; NACK received. 1100 ...
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Table 21.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0) (Continued) Values Read Current SMbus State A slave byte was transmitted NACK received. A slave byte was transmitted; 0100 ACK received. ...
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C8051T630/1/2/3/4/5 Table 21.6. SMBus Status Decoding With Hardware ACK Generation Enabled Values Read Current SMbus State A master START was gener- 1110 ated. A master data or address byte was transmitted; NACK received. 1100 ...
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Table 21.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1) (Continued) Values Read Current SMbus State A slave byte was transmitted NACK received. A slave byte was transmitted; 0100 ACK received. ...
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C8051T630/1/2/3/4/5 22. UART0 UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in Section ...
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Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in ...
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C8051T630/1/2/3/4/5 22.2. Operational Modes UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown in Figure 22.3. Figure 22.3. UART Interconnect Diagram 22.2.1. 8-Bit ...
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UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma- ble ninth data bit, and a stop bit. The state of the ninth transmit data ...
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C8051T630/1/2/3/4/5 22.3. Multiprocessor Communications 9-Bit UART mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, ...
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SFR Definition 22.1. SCON0: Serial Port 0 Control Bit 7 6 Name S0MODE MCE0 R/W R Type 0 1 Reset SFR Address = 0x98; Bit-Addressable Bit Name 7 S0MODE Serial Port 0 Operation Mode. Selects the UART0 Operation Mode. 0: ...
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C8051T630/1/2/3/4/5 SFR Definition 22.2. SBUF0: Serial (UART0) Port Data Buffer Bit 7 6 Name Type 0 0 Reset SFR Address = 0x99 Bit Name 7:0 SBUF0[7:0] Serial Data Buffer Bits 7–0 (MSB–LSB). This SFR accesses two registers; a transmit shift ...
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Table 22.1. Timer Settings for Standard Baud Rates Using The Internal 24.5 MHz Oscillator Target Baud Rate % Error Baud Rate (bps) 230400 –0.32% 115200 –0.32% 57600 0.15% 28800 –0.32% 14400 0.15% 9600 –0.32% 2400 –0.32% 1200 0.15% Notes: – ...
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C8051T630/1/2/3/4/5 23. Enhanced Serial Peripheral Interface (SPI0) The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul- ...
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Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 23.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. ...
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C8051T630/1/2/3/4/5 23.2. SPI0 Master Mode Operation A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 ...
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Master Device Figure 23.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Master Device GPIO Figure 23.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection 23.3. SPI0 Slave Mode Operation When SPI0 is enabled and not configured as ...
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C8051T630/1/2/3/4/5 3-wire slave mode is active when NSSMD1 (SPI0CN. and NSSMD0 (SPI0CN. NSS is not used in this mode, and is not mapped to an external port pin through the crossbar. Since there is no way ...
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SCK (CKPOL=0, CKPHA=0) SCK (CKPOL=0, CKPHA=1) SCK (CKPOL=1, CKPHA=0) SCK (CKPOL=1, CKPHA=1) MISO/MOSI MSB NSS (Must Remain High in Multi-Master Mode) Figure 23.5. Master Mode Data/Clock Timing SCK (CKPOL=0, CKPHA=0) SCK (CKPOL=1, CKPHA=0) MOSI MSB Bit 6 MISO MSB Bit ...
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C8051T630/1/2/3/4/5 SCK (CKPOL=0, CKPHA=1) SCK (CKPOL=1, CKPHA=1) MOSI MSB MISO MSB NSS (4-Wire Mode) Figure 23.7. Slave Mode Data/Clock Timing (CKPHA = 1) 23.6. SPI Special Function Registers SPI0 is accessed and controlled through four special function registers in the ...
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SFR Definition 23.1. SPI0CFG: SPI0 Configuration Bit 7 6 SPIBSY MSTEN CKPHA Name R R/W Type 0 0 Reset SFR Address = 0xA1 Bit Name 7 SPIBSY SPI Busy. This bit is set to logic 1 when a SPI transfer ...
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C8051T630/1/2/3/4/5 SFR Definition 23.2. SPI0CN: SPI0 Control Bit 7 6 SPIF WCOL Name R/W R/W Type 0 0 Reset SFR Address = 0xF8; Bit-Addressable Bit Name 7 SPIF SPI0 Interrupt Flag. This bit is set to logic 1 by hardware ...
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SFR Definition 23.3. SPI0CKR: SPI0 Clock Rate Bit 7 6 Name Type 0 0 Reset SFR Address = 0xA2 Bit Name 7:0 SCR[7:0] SPI0 Clock Rate. These bits determine the frequency of the SCK output when the SPI0 module is ...
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C8051T630/1/2/3/4/5 SCK* T MCKH MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 23.8. SPI Master Timing (CKPHA = 0) SCK* T MCKH T MISO MOSI * SCK is ...
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NSS SCK* T CKH MOSI T SEZ MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 23.10. SPI Slave Timing (CKPHA = 0) NSS ...
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C8051T630/1/2/3/4/5 Table 23.1. SPI Slave Timing Parameters Parameter Description Master Mode Timing (See Figure 23.8 and Figure 23.9) T SCK High Time MCKH T SCK Low Time MCKL T MISO Valid to SCK Shift Edge MIS T SCK Shift Edge ...
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Timers Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and two are 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose use. These timers can be ...
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C8051T630/1/2/3/4/5 SFR Definition 24.1. CKCON: Clock Control Bit 7 6 T3MH T3ML Name R/W R/W Type 0 0 Reset SFR Address = 0x8E Bit Name 7 T3MH Timer 3 High Byte Clock Select. Selects the clock supplied to the Timer ...
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Timer 0 and Timer 1 Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1) and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to ...
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C8051T630/1/2/3/4/5 Pre-scaled Clock SYSCLK T0 GATE0 Crossbar IN0PL XOR /INT0 Figure 24.1. T0 Mode 0 Block Diagram 24.1.2. Mode 1: 16-bit Counter/Timer Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. ...
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Mode 2: 8-bit Counter/Timer with Auto-Reload Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. TL0 holds the count and TH0 holds the reload value. When the counter ...
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C8051T630/1/2/3/4/5 24.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The coun- ter/timer in TL0 is controlled using the Timer 0 control/status bits ...
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SFR Definition 24.2. TCON: Timer Control Bit 7 6 TF1 TR1 Name R/W R/W Type 0 0 Reset SFR Address = 0x88; Bit-Addressable Bit Name 7 TF1 Timer 1 Overflow Flag. Set hardware when Timer 1 overflows. ...
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C8051T630/1/2/3/4/5 SFR Definition 24.3. TMOD: Timer Mode Bit 7 6 GATE1 C/T1 Name R/W R/W Type 0 0 Reset SFR Address = 0x89 Bit Name 7 GATE1 Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective ...
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SFR Definition 24.4. TL0: Timer 0 Low Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0x8A Bit Name 7:0 TL0[7:0] Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer 0. ...
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C8051T630/1/2/3/4/5 SFR Definition 24.6. TH0: Timer 0 High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0x8C Bit Name 7:0 TH0[7:0] Timer 0 High Byte. The TH0 register is the high byte of the 16-bit Timer ...
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Timer 2 Timer 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines the ...
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C8051T630/1/2/3/4/5 24.2.2. 8-bit Timers with Auto-Reload When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 24.5. TMR2RLL holds the reload value for TMR2L; ...
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Low-Frequency Oscillator (LFO) Capture Mode The Low-Frequency Oscillator Capture Mode allows the LFO clock to be measured against the system clock or an external oscillator source. Timer 2 can be clocked from the system clock, the system clock divided ...
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C8051T630/1/2/3/4/5 SFR Definition 24.8. TMR2CN: Timer 2 Control Bit 7 6 TF2H TF2L TF2LEN Name R/W R/W Type 0 0 Reset SFR Address = 0xC8; Bit-Addressable Bit Name 7 TF2H Timer 2 High Byte Overflow Flag. Set by hardware when ...
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SFR Definition 24.9. TMR2RLL: Timer 2 Reload Register Low Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0xCA Bit Name 7:0 TMR2RLL[7:0] Timer 2 Reload Register Low Byte. TMR2RLL holds the low byte of the reload ...
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C8051T630/1/2/3/4/5 SFR Definition 24.12. TMR2H Timer 2 High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0xCD Bit Name 7:0 TMR2H[7:0] Timer 2 Low Byte. In 16-bit mode, the TMR2H register contains the high byte of ...
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Timer 3 Timer 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T3SPLIT bit (TMR3CN.3) defines the ...
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C8051T630/1/2/3/4/5 24.3.2. 8-bit Timers with Auto-Reload When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 24.8. TMR3RLL holds the reload value for TMR3L; ...
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Low-Frequency Oscillator (LFO) Capture Mode The Low-Frequency Oscillator Capture Mode allows the LFO clock to be measured against the system clock or an external oscillator source. Timer 3 can be clocked from the system clock, the system clock divided ...
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C8051T630/1/2/3/4/5 SFR Definition 24.13. TMR3CN: Timer 3 Control Bit 7 6 TF3H TF3L TF3LEN Name R/W R/W Type 0 0 Reset SFR Address = 0x91 Bit Name 7 TF3H Timer 3 High Byte Overflow Flag. Set by hardware when the ...
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SFR Definition 24.14. TMR3RLL: Timer 3 Reload Register Low Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0x92 Bit Name 7:0 TMR3RLL[7:0] Timer 3 Reload Register Low Byte. TMR3RLL holds the low byte of the reload ...
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C8051T630/1/2/3/4/5 SFR Definition 24.17. TMR3H Timer 3 High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0x95 Bit Name 7:0 TMR3H[7:0] Timer 3 High Byte. In 16-bit mode, the TMR3H register contains the high byte of ...
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Programmable Counter Array The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer and three 16-bit capture/compare modules. Each capture/compare module has ...
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C8051T630/1/2/3/4/5 25.1. PCA Counter/Timer The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of ...
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PCA0 Interrupt Sources Figure 25.3 shows a diagram of the PCA interrupt tree. There are five independent event flags that can be used to generate a PCA0 interrupt. They are: the main PCA counter overflow flag (CF), which is ...
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C8051T630/1/2/3/4/5 25.3. Capture/Compare Modules Each module can be configured to operate independently in one of six operation modes: edge-triggered capture, software timer, high-speed output, frequency output 11-bit pulse width modulator, or 16-bit pulse width modulator. Each module has ...
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Edge-triggered Capture Mode In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA coun- ter/timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). The ...
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C8051T630/1/2/3/4/5 25.3.2. Software Timer (Compare) Mode In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. ...
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High-Speed Output Mode In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag ...
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C8051T630/1/2/3/4/5 25.3.4. Frequency Output Mode Frequency Output Mode produces a programmable-frequency square wave on the module’s associated CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the out- put is toggled. The frequency ...
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Pulse Width Modulator Mode The duty cycle of the PWM output signal in 8-bit PWM mode is varied using the module's PCA0CPLn cap- ture/compare register. When the value in the low byte of the PCA counter/timer (PCA0L) is ...
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C8051T630/1/2/3/4/5 25.3.5.2. 9/10/11-bit Pulse Width Modulator Mode The duty cycle of the PWM output signal in 9/10/11-bit PWM mode should be varied by writing to an “Auto- Reload” Register, which is dual-mapped into the PCA0CPHn and PCA0CPLn register locations. The ...