C8051T630DK Silicon Laboratories Inc, C8051T630DK Datasheet - Page 105

• Manufacturer Part Number: C8051T630DK
• Description: KIT DEV FOR C8051T630 FAMILY
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051T630DK

• Contents: Board, daughter boards, power adapter, cables, documentation and software
• Processor To Be Evaluated: C8051T63x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051T630, T631, T632, T633, T634 and T635 MCUs
• For Use With: 336-1465 - BOARD SOCKET DAUGHTER 20-QFN
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1464

19.3. Programmable Internal Low-Frequency (L-F) Oscillator
All C8051T630/1/2/3/4/5 devices include a programmable low-frequency internal oscillator, which is cali-
brated to a nominal frequency of 80 kHz. The low-frequency oscillator circuit includes a divider that can be
changed to divide the clock by 1, 2, 4, or 8, using the OSCLD bits in the OSCLCN register (see SFR Defi-
nition 19.4). Additionally, the OSCLF[3:0] bits can be used to adjust the oscillator’s output frequency.
19.3.1. Calibrating the Internal L-F Oscillator
Timers 2 and 3 include capture functions that can be used to capture the oscillator frequency, when run-
ning from a known time base. When either Timer 2 or Timer 3 is configured for L-F Oscillator Capture
Mode, a falling edge (Timer 2) or rising edge (Timer 3) of the low-frequency oscillator’s output will cause a
capture event on the corresponding timer. As a capture event occurs, the current timer value
(TMRnH:TMRnL) is copied into the timer reload registers (TMRnRLH:TMRnRLL). By recording the differ-
ence between two successive timer capture values, the low-frequency oscillator’s period can be calcu-
lated. The OSCLF bits can then be adjusted to produce the desired oscillator frequency.
SFR Definition 19.4. OSCLCN: Internal L-F Oscillator Control
SFR Address = 0xE3
Name
Reset
Bit
5:2
1:0
Type
7
6
Bit
OSCLD[1:0] Internal L-F Oscillator Divider Select.
OSCLF[3:0] Internal L-F Oscillator Frequency Control Bits.
OSCLRDY
OSCLEN
OSCLEN OSCLRDY
Name
R/W
7
0
Internal L-F Oscillator Enable.
0: Internal L-F Oscillator Disabled.
1: Internal L-F Oscillator Enabled.
Internal L-F Oscillator Ready.
0: Internal L-F Oscillator frequency not stabilized.
1: Internal L-F Oscillator frequency stabilized.
Note: OSCLRDY is only set back to 0 in the event of a device reset or a change to the
Fine-tune control bits for the Internal L-F oscillator frequency. When set to 0000b, the
L-F oscillator operates at its fastest setting. When set to 1111b, the L-F oscillator
operates at its slowest setting.
00: Divide by 8 selected.
01: Divide by 4 selected.
10: Divide by 2 selected.
11: Divide by 1 selected.
R
6
0
OSCLD[1:0] bits.
Varies
5
Varies
Rev. 1.0
4
OSCLF[3:0]
R.W
Function
Varies
3
C8051T630/1/2/3/4/5
Varies
2
1
0
OSCLD[1:0]
R/W
0
0
105