STEVAL-ISB005V1 STMicroelectronics, STEVAL-ISB005V1 Datasheet - Page 96

• Manufacturer Part Number: STEVAL-ISB005V1
• Description: BOARD EVAL CHARGER ST7260/L6924D
• Manufacturer: STMicroelectronics
• Type: Battery Managementr

Specifications of STEVAL-ISB005V1

• Main Purpose: Power Management, Battery Charger
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: L6924, ST72F63BK6M1
• Primary Attributes: 1 Cell- Li-Ion / Li-Pol, 5 V (USB Input)
• Secondary Attributes: Powered by Wall Adaptor Also, LED Status Indicators
• Input Voltage: 5 V
• Product: Power Management Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: L6924D, ST7260
• Other names: 497-8428

USB interface (USB)
Caution:
14.4.9
Note:
Note:
96/139
Table 44.
These bits are written by software. Hardware sets the STAT_TX bits to NAK when a correct
transfer has occurred (CTR=1) related to a IN or SETUP transaction addressed to this
endpoint; this allows the software to prepare the next set of data to be transmitted.
Bits 3:0 = TBC[3:0] Transmit byte count for Endpoint n.
Before transmission, after filling the transmit buffer, software must write in the TBC field the
transmit packet size expressed in bytes (in the range 0-8).
Any value outside the range 0-8 willinduce undesired effects (such as continuous data
transmission).
Endpoint n register B (EPnRB)
These registers (EP1RB and EP2RB) are used for controlling data reception on Endpoints 1
and 2. They are also reset by the USB bus reset.
Endpoint 2 and the EP2RB register are not available on some devices (see device feature
list and register map).
Bit 7 = CTRL Control.
This bit should be 0.
If this bit is 1, the Endpoint is a control endpoint. (Endpoint 0 is always a control Endpoint,
but it is possible to have more than one control Endpoint).
Bit 6 = DTOG_RX Data toggle, for reception transfers.
It contains the expected value of the toggle bit (0=DATA0, 1=DATA1) for the next data
packet. This bit is cleared by hardware in the first stage (Setup Stage) of a control transfer
(SETUP transactions start always with DATA0 PID). The receiver toggles DTOG_RX only if it
receives a correct data packet and the packet’s data PID matches the receiver sequence bit.
Bits 5:4 = STAT_RX [1:0] Status bits, for reception transfers.
These bits contain the information about the endpoint status, which are listed below:
EPnRB
CTRL
R/W
7
STAT_TX1
0
0
1
1
STAT_TX bits
DTOG
R/W
_RX
6
STAT_TX0
_RX1
STAT
R/W
5
0
1
0
1
_RX0
STAT
R/W
4
STALL: the endpoint is stalled and all transmission
VALID: this endpoint is enabled for transmission.
NAK: the endpoint is naked and all transmission
DISABLED: transmission transfers cannot be
requests result in a STALL handshake.
EA3
R/W
requests result in a NAK handshake.
3
R/W
EA2
executed.
Meaning
2
Reset value:
R/W
EA1
1
0000 xxxx (0xh)
ST7260xx
R/W
EA0
0