STEVAL-ISB005V1 STMicroelectronics, STEVAL-ISB005V1 Datasheet - Page 85
STEVAL-ISB005V1
Manufacturer Part Number
STEVAL-ISB005V1
Description
BOARD EVAL CHARGER ST7260/L6924D
Manufacturer
STMicroelectronics
Type
Battery Managementr
Specifications of STEVAL-ISB005V1
Main Purpose
Power Management, Battery Charger
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
L6924, ST72F63BK6M1
Primary Attributes
1 Cell- Li-Ion / Li-Pol, 5 V (USB Input)
Secondary Attributes
Powered by Wall Adaptor Also, LED Status Indicators
Input Voltage
5 V
Product
Power Management Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
L6924D, ST7260
Other names
497-8428
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STEVAL-ISB005V1
Manufacturer:
STMicroelectronics
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ST7260xx
13.3.3
Table 39.
Control register 2 (SCICR2)
Table 40.
SCICR2
Bit
Bit
7
6
5
4
1
0
R/W
TIE
7
Name
Name
TCIE
ILIE
PIE
RIE
TIE
PS
SCICR1 register description (continued)
SCICR2 register description
Parity Selection
Parity Interrupt Enable
Transmitter Interrupt Enable
Transmission Complete Interrupt Enable
Receiver interrupt Enable
Idle Line Interrupt Enable
TCIE
R/W
This bit selects the odd or even parity when the parity generation/detection is
enabled (PCE bit set). It is set and cleared by software. The parity will be selected
after the current byte.
0: Even parity
1: Odd parity
This bit enables the interrupt capability of the hardware parity control when a parity
error is detected (PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
1: Parity error interrupt enabled
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TDRE = 1 in the SCISR register.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC = 1 in the SCISR register.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR = 1 or RDRF = 1 in the SCISR
register.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE = 1 in the SCISR register.
6
R/W
RIE
5
R/W
ILIE
4
Function
Function
R/W
TE
Serial communications interface (SCI)
3
R/W
RE
2
Reset value:
RWU
R/W
1
0000 0000 (00h)
SBK
R/W
0
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