STEVAL-ISB005V1 STMicroelectronics, STEVAL-ISB005V1 Datasheet - Page 49

• Manufacturer Part Number: STEVAL-ISB005V1
• Description: BOARD EVAL CHARGER ST7260/L6924D
• Manufacturer: STMicroelectronics
• Type: Battery Managementr

Specifications of STEVAL-ISB005V1

• Main Purpose: Power Management, Battery Charger
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: L6924, ST72F63BK6M1
• Primary Attributes: 1 Cell- Li-Ion / Li-Pol, 5 V (USB Input)
• Secondary Attributes: Powered by Wall Adaptor Also, LED Status Indicators
• Input Voltage: 5 V
• Product: Power Management Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: L6924D, ST7260
• Other names: 497-8428

ST7260xx
12.4.3
Functional description
Counter
The main block of the programmable timer is a 16-bit free running upcounter and its
associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called
high and low.
●
●
These two read-only 16-bit registers contain the same value but with the difference that
reading the ACLR register does not clear the TOF bit (timer overflow flag), located in the
Status register (SR) (see note at the end of paragraph entitled
Writing in the CLR register or ACLR register resets the free running counter to the FFFCh
value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in
the 16-bit timer). The reset value of both counters is also FFFCh in one pulse mode and
PWM mode.
The timer clock depends on the clock control bits of the CR2 register, as illustrated in
Table
clock cycles depending on the CC[1:0] bits. The timer frequency can be f
f
CPU
/8 or an external frequency.
Counter Register (CR)
–
–
Alternate Counter Register (ACR)
–
–
32. The value in the counter register repeats every 131072, 262144 or 524288 CPU
Counter High Register (CHR) is the most significant byte (MSB)
Counter Low Register (CLR) is the least significant byte (LSB)
Alternate Counter High Register (ACHR) is the most significant byte (MSB)
Alternate Counter Low Register (ACLR) is the least significant byte (LSB)
16-bit read
Watchdog timer (WDG)
CPU
sequence).
/2, f
CPU
/4,
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