STEVAL-ISB005V1 STMicroelectronics, STEVAL-ISB005V1 Datasheet - Page 34
![BOARD EVAL CHARGER ST7260/L6924D](/photos/9/9/90910/steval-isb005v1_sml.jpg)
STEVAL-ISB005V1
Manufacturer Part Number
STEVAL-ISB005V1
Description
BOARD EVAL CHARGER ST7260/L6924D
Manufacturer
STMicroelectronics
Type
Battery Managementr
Specifications of STEVAL-ISB005V1
Main Purpose
Power Management, Battery Charger
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
L6924, ST72F63BK6M1
Primary Attributes
1 Cell- Li-Ion / Li-Pol, 5 V (USB Input)
Secondary Attributes
Powered by Wall Adaptor Also, LED Status Indicators
Input Voltage
5 V
Product
Power Management Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
L6924D, ST7260
Other names
497-8428
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STEVAL-ISB005V1
Manufacturer:
STMicroelectronics
Quantity:
1
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Power saving modes
Note:
9.3
9.4
34/139
Figure 17. Halt mode flowchart
Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during
the interrupt routine and cleared when the CC register is popped.
Slow mode
In Slow mode, the oscillator frequency can be divided by 2 as selected by the SMS bit in the
Miscellaneous Register. The CPU and peripherals are clocked at this lower frequency. Slow
mode is used to reduce power consumption, and enables the user to adapt the clock
frequency to the available supply voltage.
Wait mode
Wait mode places the MCU in a low power consumption mode by stopping the CPU.
This power saving mode is selected by calling the “WFI” ST7 software instruction.
All peripherals remain active. During Wait mode, the I bit of the CC register is forced to 0 to
enable all interrupts. All other registers and memory remain unchanged. The MCU remains
in Wait mode until an interrupt or Reset occurs, whereupon the Program Counter branches
to the starting address of the interrupt or Reset service routine.
N
INTERRUPT*
EXTERNAL
Y
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
N
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
OR SERVICE INTERRUPT
I-BIT
FETCH RESET VECTOR
HALT INSTRUCTION
4096 CPU CLOCK
CYCLES DELAY
RESET
Y
OFF
OFF
OFF
CLEARED
ON
ON
ON
SET
ST7260xx
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