STEVAL-ISB005V1 STMicroelectronics, STEVAL-ISB005V1 Datasheet - Page 59

BOARD EVAL CHARGER ST7260/L6924D

STEVAL-ISB005V1

Manufacturer Part Number
STEVAL-ISB005V1
Description
BOARD EVAL CHARGER ST7260/L6924D
Manufacturer
STMicroelectronics
Type
Battery Managementr
Datasheets

Specifications of STEVAL-ISB005V1

Main Purpose
Power Management, Battery Charger
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
L6924, ST72F63BK6M1
Primary Attributes
1 Cell- Li-Ion / Li-Pol, 5 V (USB Input)
Secondary Attributes
Powered by Wall Adaptor Also, LED Status Indicators
Input Voltage
5 V
Product
Power Management Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
L6924D, ST7260
Other names
497-8428

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STEVAL-ISB005V1
Manufacturer:
STMicroelectronics
Quantity:
1
ST7260xx
Note:
1
2
3
4
5
The OC1R register value required for a specific timing application can be calculated using
the following formula:
Where:
t
f
PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits; see
If the timer clock is an external clock the formula is:
Where:
t
f
When the value of the counter is equal to the value of the contents of the OC1R register, the
OLVL1 bit is output on the OCMP1 pin (see
The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate
an Output Compare interrupt.
When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin.
The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to
perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take
care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can
also generates interrupt if ICIE is set.
When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time has been elapsed but cannot generate an
output waveform because the level OLVL2 is dedicated to the one pulse mode.
Figure 35. One Pulse mode timing example
1. IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1
CPU
EXT
= Pulse period (in seconds)
= CPU clock frequnency (in hertz)
= Pulse period (in seconds)
= External timer clock frequency (in hertz)
Counter
OCMP1
ICAP1
IC1R
01F8
FFFC FFFD FFFE
OCiR = t
OCiR value =
OLVL2
*
f
EXT
Figure
t
- 5
PRESC
01F8
*
f
CPU
(1)
Compare1
2ED0 2ED1 2ED2
35).
- 5
OLVL1
2ED3
Watchdog timer (WDG)
FFFC FFFD
2ED3
OLVL2
Table
32)
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