ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 91

• Manufacturer Part Number: ATAVRDISPLAYX
• Description: KIT EVAL XMEGA DISPLAY
• Manufacturer: Atmel

Specifications of ATAVRDISPLAYX

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Silicon Manufacturer: Atmel
• Silicon Family Name: ATxmega
• Kit Contents: Board
• Features: Temperature Sensor, Mono Speaker Via Audio Amplifier
• Svhc: No SVHC (15-Dec-2010)
• Core Architecture: AVR
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.10.7
8077H–AVR–12/09
DFLLCTRL - DFLL Control Register
Table 7-7.
Notes:
• Bit 5 - Reserved
This bit is reserved and will always be read as zero. For compatibility with future devices, always
write this bit to zero when this register is written.
• Bit 4:0 - PLLFAC[4:0]: Multiplication Factor
The PLLFAC bits set the multiplication factor for the PLL. The multiplication factor can be in the
range from 1x to 31x. The output frequency from the PLL should not exceed 200 MHz. The PLL
must have a minimum output frequency of 10 MHz.
• Bit 7:2 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 1 - RC32MCREF: 32 MHz Calibration Reference
This bit is used to select the calibration source for the 32 MHz DFLL. By default this bit is zero
and the 32.768 kHz internal RC oscillator is selected. If this bit is set to one the 32.768 kHz Crys-
tal Oscillator connected to TOSC selected as reference. The XOSCEN bit in the CTRL register
must be set to enable the external oscillator, and the XOSCLSEL bits in the XOSCCTRL register
must be set to 32.768 kHz TOSC when this clock source is selected as the the 32 MHz DFLL
reference.
• Bit 0 - RC2MCREF: 2 MHz Calibration Reference
This bit is used to select the calibration source for the 2 MHz DFLL. By default this bit is zero and
the 32.768 kHz internal RC oscillator is selected. If this bit is set to one the 32.768 kHz Crystal
Oscillator on TOSC is selected as reference. The XOSCEN bit in the CTRL register must be set
to enable the external oscillator, and the XOSCLSEL bits in the XOSCCTRL register must be set
to 32.768 kHz TOSC when this clock source is selected as the the 2 MHz DFLL reference.
Bit
+0x06
Read/Write
Initial Value
CLKSRC[1:0]
1. 32 kHz TOSC cannot be selected as source for the PLL. An external clock must be minimum
0.4 MHz to be used as source clock.
00
01
10
11
R
7
–
0
PLL Clock Source
R
6
–
0
Group Configuration
R
5
–
0
RC32M
RC2M
XOSC
-
4
–
R
0
R
3
–
0
PLL input source
2 MHz Internal RC Oscillator
Reserved
32 MHz Internal RC Oscillator
External Clock Source
R
2
–
0
R32MCREF
R/W
1
0
(1)
RC2MCREF
XMEGA A
R/W
0
0
DFLLCTRL
91